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GLVLSI
2003
IEEE
180views VLSI» more  GLVLSI 2003»
14 years 4 months ago
3D direct vertical interconnect microprocessors test vehicle
The current trends in high performance integrated circuits are towards faster and more powerful circuits in the giga-hertz range and even further. As the more complex Integrated C...
John Mayega, Okan Erdogan, Paul M. Belemjian, Kuan...
GLVLSI
2003
IEEE
171views VLSI» more  GLVLSI 2003»
14 years 4 months ago
Combining wire swapping and spacing for low-power deep-submicron buses
We propose an approach for reducing the energy consumption of address buses that targets both the switching and the crosstalk components of power dissipation. The method is based ...
Enrico Macii, Massimo Poncino, Sabino Salerno
GLVLSI
2003
IEEE
180views VLSI» more  GLVLSI 2003»
14 years 4 months ago
A novel ultra-fast heuristic for VLSI CAD steiner trees
Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal
GLVLSI
2003
IEEE
239views VLSI» more  GLVLSI 2003»
14 years 4 months ago
A novel 32-bit scalable multiplier architecture
In this paper, we present a novel hybrid multiplier architecture that has the regularity of linear array multipliers and the performance of tree multipliers and is highly scalable...
Yeshwant Kolla, Yong-Bin Kim, John Carter
GLVLSI
2003
IEEE
151views VLSI» more  GLVLSI 2003»
14 years 4 months ago
Matrix datapath architecture for an iterative 4x4 MIMO noise whitening algorithm
Geoff Knagge, David Garrett, Sivarama Venkatesan, ...
GLVLSI
2003
IEEE
219views VLSI» more  GLVLSI 2003»
14 years 4 months ago
Buffer sizing for minimum energy-delay product by using an approximating polynomial
This paper first presents an accurate and efficient method of estimating the short circuit energy dissipation and the output transition time of CMOS buffers. Next the paper descri...
Chang Woo Kang, Soroush Abbaspour, Massoud Pedram
GLVLSI
2003
IEEE
132views VLSI» more  GLVLSI 2003»
14 years 4 months ago
A highly regular multi-phase reseeding technique for scan-based BIST
In this paper a novel reseeding architecture for scan-based BIST, which uses an LFSR as TPG, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan c...
Emmanouil Kalligeros, Xrysovalantis Kavousianos, D...
GLVLSI
2003
IEEE
130views VLSI» more  GLVLSI 2003»
14 years 4 months ago
Zero overhead watermarking technique for FPGA designs
FPGAs, because of their re-programmability, are becoming very popular for creating and exchanging VLSI intellectual properties (IPs) in the reuse-based design paradigm. Existing w...
Adarsh K. Jain, Lin Yuan, Pushkin R. Pari, Gang Qu
GLVLSI
2003
IEEE
140views VLSI» more  GLVLSI 2003»
14 years 4 months ago
A dual band CMOS VCO with a balanced duty cycle buffer
This paper proposes a dual band VCO with a standard 0.35 ㎛
Yun Cheol Han, Kwang il Kim, Jun Kim, Kwang Sub Yo...