Sciweavers

DFT
2002
IEEE
108views VLSI» more  DFT 2002»
14 years 4 months ago
A Test-Vector Generation Methodology for Crosstalk Noise Faults
Hamidreza Hashempour, Yong-Bin Kim, Nohpill Park
DFT
2002
IEEE
102views VLSI» more  DFT 2002»
14 years 4 months ago
Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems
Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-...
DFT
2002
IEEE
128views VLSI» more  DFT 2002»
14 years 4 months ago
Matrix-Based Test Vector Decompression Using an Embedded Processor
This paper describes a new compression/decompression methodology for using an embedded processor to test the other components of a system-on-a-chip (SoC). The deterministic test v...
Kedarnath J. Balakrishnan, Nur A. Touba
DFT
2002
IEEE
121views VLSI» more  DFT 2002»
14 years 4 months ago
Testing Digital Circuits with Constraints
Many digital circuits have constraints on the logic values a set of signal lines can have. In this paper, we present two new techniques for detecting the illegal combinations of l...
Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McC...
GLVLSI
2010
IEEE
138views VLSI» more  GLVLSI 2010»
14 years 4 months ago
Methodology to achieve higher tolerance to delay variations in synchronous circuits
A methodology is proposed for designing robust circuits exhibiting higher tolerance to process and environmental variations. This higher tolerance is achieved by exploiting the in...
Emre Salman, Eby G. Friedman
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
14 years 4 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
GLVLSI
2010
IEEE
210views VLSI» more  GLVLSI 2010»
14 years 4 months ago
Overscaling-friendly timing speculation architectures
Processors have traditionally been designed for the worst-case, resulting in designs that have high yields, but are expensive in terms of area and power. Better-than-worst-case (B...
John Sartori, Rakesh Kumar
GLVLSI
2010
IEEE
139views VLSI» more  GLVLSI 2010»
14 years 4 months ago
Dynamically resizable binary decision diagrams
We present the architecture of a new Ordered Binary Decision Diagram library that is designed from the ground up to be space efficient. The main novelty lies in the library’s no...
Stergios Stergiou, Jawahar Jain
GLVLSI
2010
IEEE
189views VLSI» more  GLVLSI 2010»
14 years 4 months ago
8Gb/s capacitive low power and high speed 4-PWAM transceiver design
In this paper, capacitive 4-PWAM transmitter architectures and circuits are proposed and its performances are analyzed with random jitter and PVT variation comparing with other wo...
Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi
GLVLSI
2010
IEEE
212views VLSI» more  GLVLSI 2010»
14 years 4 months ago
An integrated thermal estimation framework for industrial embedded platforms
Next generation industrial embedded platforms require the development of complex power and thermal management solutions. Indeed, an increasingly fine and intrusive thermal contro...
Andrea Acquaviva, Andrea Calimera, Alberto Macii, ...