GLVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
An effective thermal management scheme, called active bank switching, for temperature control in the register file of a microprocessor is presented. The idea is to divide the phys...
GLVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
We describe an efficient, top-down strategy for overlap removal and floorplan repair which repairs overlaps in floorplans produced by placement algorithms or rough floorplanni...
GLVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
Threshold logic is gaining prominence as an alternative to Boolean logic. The main reason for this trend is the availability of devices that implement these circuits efficiently (...
GLVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
Energy consumption is a major concern in embedded computing systems. Several studies have shown that cache memories account for about 40% or more of the total energy consumed in t...
GLVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3...
GLVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
A probabilistic power estimation technique for combinational circuits is presented. A novel set of simple waveforms is the kernel of this technique. The transition density of each...
GLVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
- The Multi-Threshold CMOS (MTCMOS) technology has become a popular technique for standby power reduction. This technology utilizes high-Vth sleep transistors to reduce subthreshol...
GLVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...
GLVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
In this paper the design of a 5 GHz wide band matched low
GLVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
In this paper, we propose a new design methodology to assess the risk for side-channel attacks, more specifically timing analysis and simple power analysis, at an early design st...