GLVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through t...
GLVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
GLVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
This paper presents a framework to design a shared memory multiprocessor on a programmable platform. We propose a complete flow, composed by a programming model and a template ar...
GLVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
A PAL-based logic block is the core of great majority of contemporary CPLD devices. The purpose of the paper is to present a new approach to multi-level synthesis for PAL-based CP...
GLVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
Compact realizations of reversible logic functions are of interest in the design of quantum computers. Such reversible functions are realized as a cascade of Toffoli gates. In th...
GLVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
GLVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
GLVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
In this paper, two new dual-path based area efficient loop filter circuits are proposed for Charge Pump Phase Locked Loop (CPPLL). The proposed circuits were designed in 0.25µ CS...
GLVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
VTS
2008
IEEE
14 years 5 months ago
2008
IEEE
Dealing with static and dynamic parameter variations has become a major challenge for design and test. To avoid unnecessary yield loss and to ensure reliable system operation a ro...