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GLVLSI
2006
IEEE
145views VLSI» more  GLVLSI 2006»
14 years 5 months ago
Leakage current starved domino logic
A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and...
Zhiyu Liu, Volkan Kursun
GLVLSI
2006
IEEE
90views VLSI» more  GLVLSI 2006»
14 years 5 months ago
Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs
This paper presents a minimum area, low-power driven clustering algorithm for coarse-grained, antifuse-based FPGAs under delay constraints. The algorithm accurately predicts logic...
Chang Woo Kang, Massoud Pedram
GLVLSI
2006
IEEE
101views VLSI» more  GLVLSI 2006»
14 years 5 months ago
A digit serial algorithm for the integer power operation
Lun Li, Mitchell A. Thornton, David W. Matula
GLVLSI
2006
IEEE
112views VLSI» more  GLVLSI 2006»
14 years 5 months ago
A design methodology for temperature variation insensitive low power circuits
Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable circuit operation under temperature fluctuations. A design methodology base...
Ranjith Kumar, Volkan Kursun
GLVLSI
2006
IEEE
113views VLSI» more  GLVLSI 2006»
14 years 5 months ago
Statistical gate delay calculation with crosstalk alignment consideration
We study gate delay variation caused by crosstalk aggressor alignment, i.e., difference of signal arrival times in coupled neighboring interconnects. This effect is as significan...
Andrew B. Kahng, Bao Liu, Xu Xu
GLVLSI
2006
IEEE
165views VLSI» more  GLVLSI 2006»
14 years 5 months ago
Block alignment in 3D floorplan using layered TCG
In modern IC design, the number of long on-chip wires has been growing rapidly because of the increasing circuit complexity. Interconnect delay has dominated over gate delay as te...
Jill H. Y. Law, Evangeline F. Y. Young, Royce L. S...
GLVLSI
2006
IEEE
110views VLSI» more  GLVLSI 2006»
14 years 5 months ago
Synthesis of a wideband low noise amplifier
Two generations of a wideband low noise amplifier (LNA) employing noise canceling principle have been synthesized. The first generation design was fabricated in a 0.35 µm SiGe Bi...
Abhishek Jajoo, Michael Sperling, Tamal Mukherjee
GLVLSI
2006
IEEE
143views VLSI» more  GLVLSI 2006»
14 years 5 months ago
SACI: statistical static timing analysis of coupled interconnects
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a s...
Hanif Fatemi, Soroush Abbaspour, Massoud Pedram, A...
GLVLSI
2006
IEEE
112views VLSI» more  GLVLSI 2006»
14 years 5 months ago
A simulation methodology for reliability analysis in multi-core SoCs
Reliability has become a significant challenge for system design in new process technologies. Higher integration levels dramatically increase power densities, which leads to high...
Ayse Kivilcim Coskun, Tajana Simunic Rosing, Yusuf...
GLVLSI
2006
IEEE
124views VLSI» more  GLVLSI 2006»
14 years 5 months ago
Dominator-based partitioning for delay optimization
Most of the logic synthesis algorithms are not scalable for large networks and, for this reason, partitioning is often applied. However traditional mincut-based partitioning techn...
David Bañeres, Jordi Cortadella, Michael Ki...