ASPDAC
2006
ACM
14 years 5 months ago
2006
ACM
— This work develops an analytic framework for clock tree analysis considering process variations that is shown to correspond well with Monte Carlo results. The analysis framewor...
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
Abstract—Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polariti...
ISVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
DATE
2007
IEEE
14 years 5 months ago
2007
IEEE
The clock tree is the interconnect net on Systems-on-Chip (SoCs) with the heaviest load and consumes up to 40% of the overall power budget. Substantial savings of the overall powe...
DATE
2009
IEEE
14 years 6 months ago
2009
IEEE
NBTI (Negative Bias Temperature Instability) has emerged as the dominant PMOS device failure mechanism for sub100nm VLSI designs. There is little research to quantify its impact o...
ISQED
2010
IEEE
14 years 6 months ago
2010
IEEE
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
DAC
2003
ACM
15 years 12 days ago
2003
ACM
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...