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ASPDAC
2006
ACM
158views Hardware» more  ASPDAC 2006»
14 years 4 months ago
Process-induced skew reduction in nominal zero-skew clock trees
— This work develops an analytic framework for clock tree analysis considering process variations that is shown to correspond well with Monte Carlo results. The analysis framewor...
Matthew R. Guthaus, Dennis Sylvester, Richard B. B...
ICCAD
2006
IEEE
132views Hardware» more  ICCAD 2006»
14 years 4 months ago
Clock buffer polarity assignment for power noise reduction
Abstract—Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polariti...
Rupak Samanta, Ganesh Venkataraman, Jiang Hu
ISVLSI
2007
IEEE
184views VLSI» more  ISVLSI 2007»
14 years 5 months ago
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
DATE
2007
IEEE
109views Hardware» more  DATE 2007»
14 years 5 months ago
System level clock tree synthesis for power optimization
The clock tree is the interconnect net on Systems-on-Chip (SoCs) with the heaviest load and consumes up to 40% of the overall power budget. Substantial savings of the overall powe...
Saif Ali Butt, Stefan Schmermbeck, Jurij Rosenthal...
DATE
2009
IEEE
122views Hardware» more  DATE 2009»
14 years 5 months ago
Analysis and optimization of NBTI induced clock skew in gated clock trees
NBTI (Negative Bias Temperature Instability) has emerged as the dominant PMOS device failure mechanism for sub100nm VLSI designs. There is little research to quantify its impact o...
Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram...
ISQED
2010
IEEE
227views Hardware» more  ISQED 2010»
14 years 5 months ago
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, ...
DAC
2003
ACM
14 years 11 months ago
Clock-tree power optimization based on RTL clock-gating
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...
Monica Donno, Alessandro Ivaldi, Luca Benini, Enri...