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DATE
2003
IEEE
82views Hardware» more  DATE 2003»
14 years 5 months ago
Scaling into Ambient Intelligence
Envision the situation that high quality information and entertainment is easily accessible to anyone, anywhere, at any time, and on any device. How realistic is this vision? And ...
Twan Basten, Luca Benini, Anantha Chandrakasan, Me...
DATE
2003
IEEE
105views Hardware» more  DATE 2003»
14 years 5 months ago
Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation
: Stresses are considered an integral part of any modern industrial DRAM test. This paper describes a novel method to optimize stresses for memory testing, using defect injection a...
Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev...
DATE
2003
IEEE
84views Hardware» more  DATE 2003»
14 years 5 months ago
PARLAK: Parametrized Lock Cache Generator
A system-on-chip lock cache (SoCLC) is an intellectual property (IP) core that provides effective lock synchronization in a heterogeneous multiprocessor shared-memory system-on-ac...
Bilge Saglam Akgul, Vincent John Mooney III
DATE
2003
IEEE
152views Hardware» more  DATE 2003»
14 years 5 months ago
Bluetooth Transceiver Design with VHDL-AMS
This paper describes the design challenges of BlueTraCTM , a low-cost, low-power radio transceiver and the usage of mixed-signal/mixed-mode techniques and behavioral modeling with...
Rami Ahola, Daniel Wallner, Marius Sida
DATE
2003
IEEE
90views Hardware» more  DATE 2003»
14 years 5 months ago
Extending JTAG for Testing Signal Integrity in SoCs
As the technology is shrinking and the working frequency is going into multi gigahertz range, the issues related to interconnect testing are becoming more dominant. Specifically,...
Nisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nour...
DATE
2003
IEEE
127views Hardware» more  DATE 2003»
14 years 5 months ago
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
Amit Agarwal, Kaushik Roy, T. N. Vijaykumar
DATE
2003
IEEE
134views Hardware» more  DATE 2003»
14 years 5 months ago
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration
The design of high performance multimedia systems in a short time force us to use IP's blocks in many designs. However, their correct integration in a design implies more com...
Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Ri...
DATE
2003
IEEE
116views Hardware» more  DATE 2003»
14 years 5 months ago
Statistical Timing Analysis Using Bounds
The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing anal...
Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sar...
DATE
2003
IEEE
151views Hardware» more  DATE 2003»
14 years 5 months ago
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
Adrijean Andriahantenaina, Hervé Charlery, ...