DATE
2003
IEEE
14 years 5 months ago
2003
IEEE
We propose a technique for compressing test vectors. The technique reduces test application time and tester memory requirements by utilizing part of the predecessor response in co...
DATE
2003
IEEE
14 years 5 months ago
2003
IEEE
Given the growth in application-specific processors, there is a strong need for a retargetable modeling framework that is capable of accurately capturing complex processor behavi...
DATE
2003
IEEE
14 years 5 months ago
2003
IEEE
Abstract : A novel design methodology for test pattern generation in BIST is presented. Here faults and errors in the generator itself are detected. Two different design methodolog...
DATE
2003
IEEE
14 years 5 months ago
2003
IEEE
1 We present an approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of timetriggered and event-triggered clusters, interc...
DATE
2003
IEEE
14 years 5 months ago
2003
IEEE
We investigate a characterization of hard-to-detect bridging faults. For circuits with large numbers of lines (or nodes), this characterization can be used to select target faults...
DATE
2003
IEEE
14 years 5 months ago
2003
IEEE
We propose a new approach to test generation and test compaction for scan circuits that eliminates the distinction between scan operations and application of primary input vectors...
DATE
2003
IEEE
14 years 5 months ago
2003
IEEE
DATE
2003
IEEE
14 years 5 months ago
2003
IEEE
More and more the system verification makes use of hardware emulation techniques that allow a speed up in simulation performance up to thousand times. Typically, a design is comp...
DATE
2003
IEEE
14 years 5 months ago
2003
IEEE
DATE
2003
IEEE
14 years 5 months ago
2003
IEEE
This work presents a soft IP description of Rijndael, the Advanced Encryption Standard (AES) of National Institute of Standards and Technology (NIST). This Rijndael implementation...