Sciweavers

DATE
2003
IEEE
102views Hardware» more  DATE 2003»
14 years 2 months ago
Non-Enumerative Path Delay Fault Diagnosis
The first non-enumerative framework for diagnosing path delay faults using zero suppressed binary decision diagrams is introduced. We show that fault free path delay faults with ...
Saravanan Padmanaban, Spyros Tragoudas
DATE
2003
IEEE
131views Hardware» more  DATE 2003»
14 years 2 months ago
High Speed and Highly Testable Parallel Two-Rail Code Checker
In this article we propose a high speed and highly testable parallel two-rail code checker, which features a compact structure and is Totally-Self-Checking or Strongly Code-Disjoi...
Martin Omaña, Daniele Rossi, Cecilia Metra
DATE
2003
IEEE
138views Hardware» more  DATE 2003»
14 years 2 months ago
Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric
There have been several recent attempts to include duplication-based on-line testability in behaviourally synthesized designs. In this paper, on-line testability is considered wit...
Petros Oikonomakos, Mark Zwolinski, Bashir M. Al-H...
DATE
2003
IEEE
92views Hardware» more  DATE 2003»
14 years 2 months ago
Local Search for Boolean Relations on the Basis of Unit Propagation
We propose a method for local search of Boolean relations relating variables of a CNF formula. The method is to branch on small subsets of the set of CNF variables and to analyze ...
Yakov Novikov
DATE
2003
IEEE
93views Hardware» more  DATE 2003»
14 years 2 months ago
Comparison of Test Pattern Decompression Techniques
Test pattern decompression techniques are bounded with the algorithm of test pattern ordering and test data flow controlling. Some of the methods could have more sophisticated sor...
Ondrej Novák
DATE
2003
IEEE
99views Hardware» more  DATE 2003»
14 years 2 months ago
Load Distribution with the Proximity Congestion Awareness in a Network on Chip
In Networks on Chip, NoC, very low cost and high performance switches will be of critical importance. For a regular two-dimensional NoC we propose a very simple, memoryless switch...
Erland Nilsson, Mikael Millberg, Johnny Öberg...
DATE
2003
IEEE
102views Hardware» more  DATE 2003»
14 years 2 months ago
Power Constrained High-Level Synthesis of Battery Powered Digital Systems
We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle co...
S. F. Nielsen, Jan Madsen
DATE
2003
IEEE
105views Hardware» more  DATE 2003»
14 years 2 months ago
Detecting Soft Errors by a Purely Software Approach: Method, Tools and Experimental Results
In this paper is described a software technique allowing to detect soft errors occurring in processor-based digital architectures. The detection mechanism is based on a set of rul...
B. Nicolescu, Raoul Velazco
DATE
2003
IEEE
145views Hardware» more  DATE 2003»
14 years 2 months ago
Optimal Reconfiguration Functions for Column or Data-bit Built-In Self-Repair
In modern SoCs, embedded memories occupy the largest part of the chip area and include an even larger amount of active devices. As memories are designed very tightly to the limits...
Michael Nicolaidis, Nadir Achouri, Slimane Boutobz...
DATE
2003
IEEE
94views Hardware» more  DATE 2003»
14 years 2 months ago
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors
Modern embedded processors use data caches with higher and higher degrees of associativity in order to increase performance. A set–associative data cache consumes a significant...
Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru...