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DATE
2003
IEEE
69views Hardware» more  DATE 2003»
14 years 4 months ago
Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information
In today’s deep-submicron designs, the interconnect delays contribute an increasing part to the overall performance of an implementation. Particularly when targeting field prog...
Ulrich Seidl, Klaus Eckl, Frank M. Johannes
DATE
2003
IEEE
84views Hardware» more  DATE 2003»
14 years 4 months ago
SoC Design and Test Considerations
: Modern SoC Design for high-volume products requires a strong focus on Design-for-Test and Designfor-Manufacturability. We present a case study of an SoC test concept, including a...
Martin Schrader, Roderick McConnell
DATE
2003
IEEE
99views Hardware» more  DATE 2003»
14 years 4 months ago
Instruction Set Emulation for Rapid Prototyping of SoCs
In this paper the application of Instruction Set Emulation for rapid prototyping of SoCs will be presented. The emulation works in a way that both the software and the hardware be...
Jürgen Schnerr, Gunter Haug, Wolfgang Rosenst...
DATE
2003
IEEE
80views Hardware» more  DATE 2003»
14 years 4 months ago
Consequences of RAM Bitline Twisting for Test Coverage
Ivo Schanstra, A. J. van de Goor
DATE
2003
IEEE
115views Hardware» more  DATE 2003»
14 years 4 months ago
Embedded Software in Digital AM-FM Chipset
The new standard DRM for digital radio broadcast in AM band requires integrated devices for radio receivers at low cost and very low power consumption. A chipset is currently desi...
Michel Sarlotte, Bernard Candaele, J. Quevremont, ...
DATE
2003
IEEE
65views Hardware» more  DATE 2003»
14 years 4 months ago
Masking the Energy Behavior of DES Encryption
Smart cards are vulnerable to both invasive and non-invasive attacks. Specifically, non-invasive attacks using power and timing measurements to extract the cryptographic key has d...
Hendra Saputra, Narayanan Vijaykrishnan, Mahmut T....
DATE
2003
IEEE
62views Hardware» more  DATE 2003»
14 years 4 months ago
RTL Test Pattern Generation for High Quality Loosely Deterministic BIST
Marcelino B. Santos, José M. Fernandes, Isa...
DATE
2003
IEEE
116views Hardware» more  DATE 2003»
14 years 4 months ago
Development and Application of Design Transformations in ForSyDe
The ForSyDe methodology has been developed for system level design. Starting with a formal specification model, that captures the functionality of the system at a high abstractio...
Ingo Sander, Axel Jantsch, Zhonghai Lu
DATE
2003
IEEE
145views Hardware» more  DATE 2003»
14 years 4 months ago
Automated Bus Generation for Multiprocessor SoC Design
The performance of a system, especially a multiprocessor system, heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custo...
Kyeong Keol Ryu, Vincent John Mooney