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DATE
2006
IEEE
112views Hardware» more  DATE 2006»
14 years 5 months ago
Simultaneously improving code size, performance, and energy in embedded processors
Code size and energy consumption are critical design concerns for embedded processors as they determine the cost of the overall system. Techniques such as reduced length instructi...
Ahmad Zmily, Christos Kozyrakis
DATE
2006
IEEE
80views Hardware» more  DATE 2006»
14 years 5 months ago
Software-based self-test of processors under power constraints
Software-based self-test (SBST) of processors offers many benefits, such as dispense with expensive test equipments, test execution during maintenance and in the field or initiali...
Jun Zhou, Hans-Joachim Wunderlich
DATE
2006
IEEE
94views Hardware» more  DATE 2006»
14 years 5 months ago
Large power grid analysis using domain decomposition
: This paper presents a domain decomposition (DD) technique for efficient simulation of large-scale linear circuits such as power distribution networks. Simulation results show th...
Quming Zhou, Kai Sun, Kartik Mohanram, Danny C. So...
DATE
2006
IEEE
105views Hardware» more  DATE 2006»
14 years 5 months ago
Statistical timing analysis with path reconvergence and spatial correlations
State of the art statistical timing analysis (STA) tools often yield less accurate results when timing variables become correlated. Spatial correlation and correlation caused by p...
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
DATE
2006
IEEE
151views Hardware» more  DATE 2006»
14 years 5 months ago
An 830mW, 586kbps 1024-bit RSA chip design
This paper presents an RSA hardware design that simultaneously achieves high-performance and lowpower. A bit-oriented, split modular multiplication algorithm and architecture are ...
Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shy...
DATE
2006
IEEE
73views Hardware» more  DATE 2006»
14 years 5 months ago
Double-sampling single-loop sigma-delta modulator topologies for broadband applications
This paper presents novel double sampling high order single-loop sigma-delta modulator structures for wideband applications. To alleviate the quantization noise folding into the i...
Mohammad Yavari, Omid Shoaei, Ángel Rodr&ia...
DATE
2006
IEEE
116views Hardware» more  DATE 2006»
14 years 5 months ago
Systematic and optimal design of CMOS two-stage opamps with hybrid cascode compensation
This paper presents a systematic and optimal design of hybrid cascode compensation method which is used in fully differential two-stage CMOS operational transconductance amplifier...
Mohammad Yavari, Omid Shoaei, Ángel Rodr&ia...
DATE
2006
IEEE
82views Hardware» more  DATE 2006»
14 years 5 months ago
Concurrent core test for SOC using shared test set and scan chain disable
A concurrent core test approach is proposed to reduce the test cost of SOC. Multiple cores in SOC can be tested simultaneously by using a shared test set and scan chain disable. P...
Gang Zeng, Hideo Ito
DATE
2006
IEEE
107views Hardware» more  DATE 2006»
14 years 5 months ago
Time domain model order reduction by wavelet collocation method
In this paper, a wavelet based approach is proposed for the model order reduction of linear circuits in time domain. Compared with Chebyshev reduction method, the wavelet reductio...
Xuan Zeng, Lihong Feng, Yangfeng Su, Wei Cai, Dian...
DATE
2006
IEEE
112views Hardware» more  DATE 2006»
14 years 5 months ago
On the verification of automotive protocols
Verification quality is a must for functional safety in electronic systems. In automotive, the verification flow is historically based on a layered approach, where each level (mod...
G. Zarri, F. Colucci, F. Dupuis, R. Mariani, M. Pa...