Sciweavers

DATE
2006
IEEE
101views Hardware» more  DATE 2006»
14 years 5 months ago
A parallel configuration model for reducing the run-time reconfiguration overhead
Multitasking on reconfigurable logic can achieve very high silicon reusability. However, configuration latency is a major limitation and it can largely degrade the system performa...
Yang Qu, Juha-Pekka Soininen, Jari Nurmi
DATE
2006
IEEE
105views Hardware» more  DATE 2006»
14 years 5 months ago
Comfortable modeling of complex reactive systems
Modeling systems based on semi-formal graphical formalisms, such as Statecharts, has become standard practice in the design of reactive embedded devices. However, the modeling of ...
Steffen Prochnow, Reinhard von Hanxleden
DATE
2006
IEEE
108views Hardware» more  DATE 2006»
14 years 5 months ago
Test compaction for transition faults under transparent-scan
Transparent-scan was proposed as an approach to test generation and test compaction for scan circuits. Its effectiveness was demonstrated earlier in reducing the test application ...
Irith Pomeranz, Sudhakar M. Reddy
DATE
2006
IEEE
89views Hardware» more  DATE 2006»
14 years 5 months ago
Generation of broadside transition fault test sets that detect four-way bridging faults
Generation of n -detection test sets is typically done for a single fault model. In this work we investigate the generation of n -detection test sets by pairing each fault of a ta...
Irith Pomeranz, Sudhakar M. Reddy
DATE
2006
IEEE
78views Hardware» more  DATE 2006»
14 years 5 months ago
Functional constraints vs. test compression in scan-based delay testing
We present an approach to prevent overtesting in scan-based delay test. The test data is transformed with respect to functional constraints while simultaneously keeping as many po...
Ilia Polian, Hideo Fujiwara
DATE
2006
IEEE
91views Hardware» more  DATE 2006»
14 years 5 months ago
A dynamically reconfigurable packet-switched network-on-chip
Thilo Pionteck, Carsten Albrecht, Roman Koch
DATE
2006
IEEE
130views Hardware» more  DATE 2006»
14 years 5 months ago
Automatic run-time selection of power policies for operating systems
A significant volume of research has concentrated on operating-system directed power management (OSPM). The primary focus of previous research has been the development of OSPM po...
Nathaniel Pettis, Jason Ridenour, Yung-Hsiang Lu
DATE
2006
IEEE
100views Hardware» more  DATE 2006»
14 years 5 months ago
Heterogeneous behavioral hierarchy for system level designs
Enhancing productivity for designing complex embedded systems requires system level design methodology and language support for capturing complex design in high level models. For ...
Hiren D. Patel, Sandeep K. Shukla, Reinaldo A. Ber...
DATE
2006
IEEE
114views Hardware» more  DATE 2006»
14 years 5 months ago
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC
Memory and communication architectures have a significant impact on the cost, performance, and time-to-market of complex multi-processor system-on-chip (MPSoC) designs. The memory...
Sudeep Pasricha, Nikil D. Dutt
DATE
2006
IEEE
82views Hardware» more  DATE 2006»
14 years 5 months ago
Dynamic code overlay of SDF-modeled programs on low-end embedded systems
In this paper we propose a dynamic code overlay technique of synchronous data-flow (SDF) –modeled program for low-end embedded systems which lack MMUsupport. With this technique...
Hae-woo Park, Kyoungjoo Oh, Soyoung Park, Myoung-m...