Sciweavers

DATE
2006
IEEE
121views Hardware» more  DATE 2006»
14 years 5 months ago
Analysis of the impact of bus implemented EDCs on on-chip SSN
In this paper we analyze the impact of error detecting codes, implemented on an on-chip bus, on the on-chip simultaneous switching noise (SSN). First, we analyze in detail how SSN...
Daniele Rossi, Carlo Steiner, Cecilia Metra
DATE
2006
IEEE
134views Hardware» more  DATE 2006»
14 years 5 months ago
Energy efficiency vs. programmability trade-off: architectures and design principles
Pablo Robelly, Hendrik Seidel, K. C. Chen, Gerhard...
DATE
2006
IEEE
92views Hardware» more  DATE 2006»
14 years 5 months ago
Priority scheduling in digital microfluidics-based biochips
Discrete droplet digital microfluidics-based biochips face problems similar to that in other VLSI CAD systems, but with new constraints and interrelations. We focus on one such pr...
Andrew J. Ricketts, Kevin M. Irick, Narayanan Vija...
DATE
2006
IEEE
91views Hardware» more  DATE 2006»
14 years 5 months ago
How OEMs and suppliers can face the network integration challenges
Systems integration is a major challenge in many industries. Systematic analysis of the complex integration effects, especially with respect to timing and performance, significant...
Kai Richter, Rolf Ernst
DATE
2006
IEEE
94views Hardware» more  DATE 2006»
14 years 5 months ago
Sociology of design and EDA
Walden C. Rhines
DATE
2006
IEEE
153views Hardware» more  DATE 2006»
14 years 5 months ago
Analyzing timing uncertainty in mesh-based clock architectures
Mesh architectures are used to distribute critical global signals on a chip, such as clock and power/ground. Redundancy created by mesh loops smooths out undesirable variations be...
Subodh M. Reddy, Gustavo R. Wilke, Rajeev Murgai
DATE
2006
IEEE
114views Hardware» more  DATE 2006»
14 years 5 months ago
An efficient static algorithm for computing the soft error rates of combinational circuits
Soft errors have emerged as an important reliability challenge for nanoscale VLSI designs. In this paper, we present a fast and efficient soft error rate (SER) computation algorit...
Rajeev R. Rao, Kaviraj Chopra, David Blaauw, Denni...
DATE
2006
IEEE
159views Hardware» more  DATE 2006»
14 years 5 months ago
Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors
Reduced energy consumption is one of the most important design goals for embedded application domains like wireless, multimedia and biomedical. Instruction memory hierarchy has be...
Praveen Raghavan, Andy Lambrechts, Murali Jayapala...
DATE
2006
IEEE
91views Hardware» more  DATE 2006»
14 years 5 months ago
Customization of application specific heterogeneous multi-pipeline processors
Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswar...
DATE
2006
IEEE
92views Hardware» more  DATE 2006»
14 years 5 months ago
Space-efficient FPGA-accelerated collision detection for virtual prototyping
Andreas Raabe, Stefan Hochgürtel, Joachim K. ...