Abstract— Continuing scaling of CMOS technology has allowed aggressive pursuant of increased clock rate in DSM chips. The ever shorter clock period has made switching times of di...
—Optimizing sequential cycles is essential for many types of high-performance circuits, such as pipelines for packet processing. Retiming is a powerful technique for speeding pip...
Cristian Soviani, Olivier Tardieu, Stephen A. Edwa...
: In this research, a fixed-point multimedia co-processor is designed and tested into an ARM-10 based mobile graphics processor for portable 2-D and 3-D multimedia applications. Th...
In this paper we present a method which allows the statistical analysis of nanoelectronic Boolean networks with respect to timing uncertainty and noise. All signals are considered...
Oliver Soffke, Peter Zipf, Tudor Murgan, Manfred G...
We present a de-layered protocol engine for termination of 40Gbps TCP connections using a reconfigurable FPGA silicon platform. This protocol engine is designed for a planned att...
In many computer systems with large data computations, the delay of memory access is one of the major performance bottlenecks. In this paper, we propose an enhanced field remappi...
Keoncheol Shin, Jungeun Kim, Seonggun Kim, Hwansoo...
Abstract: This paper addresses the problem of equivalence verification of RTL descriptions that implement arithmetic computations (add, mult, shift) over bitvectors that have di...
This paper presents a configurable and generic platform architecture suitable to interface several kinds of sensors for automotive applications. A platform-based design approach i...