Sciweavers

DAC
1998
ACM
14 years 9 months ago
Layout Techniques for Minimizing On-Chip Interconnect Self Inductance
Because magnetic e ects have a much longer spatial range than electrostatic e ects, an interconnect line with large inductance will be sensitive to distant variations in interconn...
Yehia Massoud, Steve S. Majors, Tareq Bustami, Jac...
DAC
1998
ACM
14 years 9 months ago
A Mixed Nodal-Mesh Formulation for Efficient Extraction and Passive Reduced-Order Modeling of 3D Interconnects
As VLSI circuit speeds have increased, reliable chip and system design can no longer be performed without accurate threedimensional interconnect models. In this paper, we describe...
Nuno Alexandre Marques, Mattan Kamon, Jacob White,...
DAC
1998
ACM
14 years 9 months ago
Multi-Pad Power/Ground Network Design for Uniform Distribution of Ground Bounce
This paper presents a method for power and ground (p/g) network routing for high speed CMOS chips with multiple p/g pads. Our objective is not to reduce the total amount of the gr...
Jaewon Oh, Massoud Pedram
DAC
1998
ACM
14 years 9 months ago
Design Reliability - Estimation through Statistical Analysis of Bug Discovery Data
Statistical analysis of bug discovery data is used in the software industry to check the quality of the testing process and estimate the reliability of the tested program. In this...
Yossi Malka, Avi Ziv
DAC
1998
ACM
14 years 9 months ago
Software Synthesis of Process-Based Concurrent Programs
We present a Petri net theoretic approach to the software synthesis problem that can synthesize ordinary C programs from processbased concurrent specifications without the need for...
Bill Lin
DAC
1998
ACM
14 years 9 months ago
Code Compression for Embedded Systems
Memory is one of the most restricted resources in many modern embedded systems. Code compression can provide substantial savings in terms of size. In a compressed code CPU, a cach...
Haris Lekatsas, Wayne Wolf
DAC
1998
ACM
14 years 9 months ago
Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs
The logic blocks CLBs of a lookup table LUT based FPGA consist of one or more LUTs, possibly of di erent sizes. In this paper, we focus on technology mapping for CLBs with several...
Madhukar R. Korupolu, K. K. Lee, D. F. Wong
DAC
1998
ACM
14 years 9 months ago
Efficient Coloring of a Large Spectrum of Graphs
We have developed a new algorithm and software for graph coloring by systematically combining several algorithm and software development ideas that had crucial impact on the algor...
Darko Kirovski, Miodrag Potkonjak