Sciweavers

DAC
2007
ACM
15 years 16 days ago
Gate Sizing For Cell Library-Based Designs
With increasing time-to-market pressure and shortening semiconductor product cycles, more and more chips are being designed with library-based methodologies. In spite of this shif...
Shiyan Hu, Mahesh Ketkar, Jiang Hu
DAC
2007
ACM
15 years 16 days ago
Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation
We present an efficient technique for finding the mean and variance of the full-chip leakage of a candidate design, while considering logic-structures and both die-to-die and with...
Khaled R. Heloue, Navid Azizi, Farid N. Najm
DAC
2007
ACM
15 years 16 days ago
High Performance and Low Power Electronics on Flexible Substrate
We propose a design and optimization methodology for high performance and ultra low power digital applications on flexible substrate using Low Temperature Polycrystalline Silicon ...
Jing Li, Kunhyuk Kang, Aditya Bansal, Kaushik Roy
DAC
2007
ACM
15 years 16 days ago
Reducing Data-Memory Footprint of Multimedia Applications by Delay Redistribution
It is now common for multimedia applications to be partitioned and mapped onto multiple processing elements of a system-on-chip architecture. An important design constraint in suc...
Balaji Raman, Samarjit Chakraborty, Wei Tsang Ooi,...
DAC
2007
ACM
15 years 16 days ago
Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis
It is known that ramp-based models are not sufficient for accurate timing modeling. In this paper, we develop a technique that accurately models the waveforms, and also allows a f...
Anand Ramalingam, Ashish Kumar Singh, Sani R. Nass...
DAC
2007
ACM
15 years 16 days ago
Fast Min-Cost Buffer Insertion under Process Variations
Process variation has become a critical problem in modern VLSI fabrication. In the presence of process variation, buffer insertion problem under performance constraints becomes mo...
Ruiming Chen, Hai Zhou
DAC
2007
ACM
15 years 16 days ago
MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs
In this paper, we present a new multi-packing tree (MP-tree) representation for macro placement to handle mixed-size designs. Based on binary trees, the MP-tree is very efficient,...
Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu...
DAC
2007
ACM
15 years 16 days ago
PV-PPV: Parameter Variability Aware, Automatically Extracted, Nonlinear Time-Shifted Oscillator Macromodels
Abstract-- The PPV is a robust phase domain macromodel for oscillators. It has been proven to predict oscillators' responses correctly under small signal perturbations, and ca...
Zhichun Wang, Xiaolue Lai, Jaijeet S. Roychowdhury
DAC
2007
ACM
15 years 16 days ago
Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations
Due to increased variability trends in nanoscale integrated circuits, statistical circuit analysis has become essential. We present a novel method for post-silicon analysis that g...
Qunzeng Liu, Sachin S. Sapatnekar
DAC
2007
ACM
15 years 16 days ago
RISPP: Rotating Instruction Set Processing Platform
Adaptation in embedded processing is key in order to address efficiency. The concept of extensible embedded processors works well if a few a-priori known hot spots exist. However,...
Jörg Henkel, Lars Bauer, Muhammad Shafique, S...