ETS
2006
IEEE
14 years 7 months ago
2006
IEEE
This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. strate that these interconnects abstract the interconne...
ETS
2006
IEEE
14 years 7 months ago
2006
IEEE
A central problem in built-in self test (BIST) is how to efficiently generate a small set of test vectors that detect all targeted faults. We propose a novel solution that uses l...
ETS
2006
IEEE
14 years 7 months ago
2006
IEEE
The application of Dynamic Voltage Scaling (DVS) to reduce energy consumption may have a detrimental impact on the quality of manufacturing tests employed to detect permanent faul...
ETS
2006
IEEE
14 years 7 months ago
2006
IEEE
— Accurate generation of circuit specifications from test signatures is a difficult problem, since analytical expressions cannot precisely describe the nonlinear relationships ...
ETS
2006
IEEE
14 years 7 months ago
2006
IEEE
ETS
2006
IEEE
14 years 7 months ago
2006
IEEE
The Networks-on-Chip (NoCs) paradigm is emerging as a solution for the communication of SoCs. Many NoC architecture propositions are presented but few works on testing these netwo...
ETS
2006
IEEE
14 years 7 months ago
2006
IEEE
ETS
2006
IEEE
14 years 7 months ago
2006
IEEE
In this paper we address the test scheduling problem for Builtin Self-tested (BISTed) embedded SRAMs (e-SRAMs) when Data Retention Faults (DRFs) are considered. The proposed test ...
ETS
2006
IEEE
14 years 7 months ago
2006
IEEE
- The resources available on a chip continue to grow, following Moore's Law. However, the major process by which the benefits of Moore's Law accrue, which is the continui...
ETS
2006
IEEE
14 years 7 months ago
2006
IEEE
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...