Sciweavers

FCCM
2006
IEEE
127views VLSI» more  FCCM 2006»
14 years 6 months ago
Scalable Softcore Vector Processor for Biosequence Applications
Arpith C. Jacob, Brandon Harris, Jeremy Buhler, Ro...
FCCM
2006
IEEE
120views VLSI» more  FCCM 2006»
14 years 6 months ago
FPGAs, GPUs and the PS2 - A Single Programming Methodology
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony’s Playstation 2 vector units offer scope for hardware acceleration of applications. Implementin...
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckm...
FCCM
2006
IEEE
105views VLSI» more  FCCM 2006»
14 years 6 months ago
Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs
Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Ste...
FCCM
2006
IEEE
137views VLSI» more  FCCM 2006»
14 years 6 months ago
Single Pass, BLAST-Like, Approximate String Matching on FPGAs
Abstract: Approximate string matching is fundamental to bioinformatics, and has been the subject of numerous FPGA acceleration studies. We address issues with respect to FPGA imple...
Martin C. Herbordt, Josh Model, Yongfeng Gu, Bhara...
FCCM
2006
IEEE
119views VLSI» more  FCCM 2006»
14 years 6 months ago
Integrating FPGA Acceleration into the Protomol Molecular Dynamics Code: Preliminary Report
: We describe a new pipeline for computing non-bonded forces and its integration into the ProtoMol molecular dynamics (MD) code. There are several innovations: a novel interpolatio...
Yongfeng Gu, Tom Van Court, Martin C. Herbordt
FCCM
2006
IEEE
125views VLSI» more  FCCM 2006»
14 years 6 months ago
A Multithreaded Soft Processor for SoPC Area Reduction
The growth in size and performance of Field Programmable Gate Arrays (FPGAs) has compelled System-on-aProgrammable-Chip (SoPC) designers to use soft processors for controlling sys...
Blair Fort, Davor Capalija, Zvonko G. Vranesic, St...
FCCM
2006
IEEE
268views VLSI» more  FCCM 2006»
14 years 6 months ago
Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAs
We present an architecture and an implementation of an FPGA-based sparse matrix-vector multiplier (SMVM) for use in the iterative solution of large, sparse systems of equations ar...
Yousef El-Kurdi, Warren J. Gross, Dennis Giannacop...
FCCM
2006
IEEE
144views VLSI» more  FCCM 2006»
14 years 6 months ago
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
Robert G. Dimond, Oskar Mencer, Wayne Luk
FCCM
2006
IEEE
108views VLSI» more  FCCM 2006»
14 years 6 months ago
A Reconfigurable Distributed Computing Fabric Exploiting Multilevel Parallelism
This paper presents a novel reconfigurable data flow processing architecture that promises high performance by explicitly targeting both fine- and course-grained parallelism. This...
Charles L. Cathey, Jason D. Bakos, Duncan A. Buell
FCCM
2006
IEEE
107views VLSI» more  FCCM 2006»
14 years 6 months ago
Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths
Field-Programmable Gate Arrays (FPGAs) are being employed in high performance computing systems owing to their potential to accelerate a wide variety of long-running routines. Par...
Uday Bondhugula, Ananth Devulapalli, James Dinan, ...