ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
Industry has shifted towards multi-core designs as we have hit the memory and power walls. However, single thread performance remains of paramount importance since some applicatio...
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
Recent research advocates memory streaming techniques to alleviate the performance bottleneck caused by the high latencies of off-chip memory accesses. Temporal memory streaming r...
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
The advent of multicores has introduced new challenges for programmers to provide increased performance and software reliability. There has been significant interest in technique...
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
Many multi-core processors employ a large last-level cache (LLC) shared among the multiple cores. Past research has demonstrated that sharing-oblivious cache management policies (...
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies, such as DRAM. In contrast, phase change memory (PCM)...