MICRO
2009
IEEE
14 years 7 months ago
2009
IEEE
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
MICRO
2009
IEEE
14 years 7 months ago
2009
IEEE
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
Detecting data races in parallel programs is important for both software development and production-run diagnosis. Recently, there have been several proposals for hardware-assiste...
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
While Moore’s Law predicts the ability of semi-conductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in t...
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
Dynamic voltage and frequency scaling (DVFS) is a commonly-used powermanagement scheme that dynamically adjusts power and performance to the time-varying needs of running programs...
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable c...
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
The incidence of hard errors in CPUs is a challenge for future multicore designs due to increasing total core area. Even if the location and nature of hard errors are known a prio...
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...