ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. A...
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
Data prefetching has long been an important technique to amortize the effects of the memory wall, and is likely to remain so in the current era of multi-core systems. Most prefetc...
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
Analysis of technology and application trends reveals a growing imbalance in the peak compute-to-memory-capacity ratio for future servers. At the same time, the fraction contribut...
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
Shared-memory multi-threaded programming is inherently more difficult than single-threaded programming. The main source of complexity is that, the threads of an application can in...
ISCA
2009
IEEE
14 years 7 months ago
2009
IEEE
In the near term, Moore’s law will continue to provide an increasing number of transistors and therefore an increasing number of on-chip cores. Limited pin bandwidth prevents th...
IEEEPACT
2009
IEEE
14 years 7 months ago
2009
IEEE
Translation Lookaside Buffers (TLBs) are a staple in modern computer systems and have a significant impact on overall system performance. Numerous prior studies have addressed TL...
IEEEPACT
2009
IEEE
14 years 7 months ago
2009
IEEE
Abstract—This paper proposes a new software-oriented approach for managing the distributed shared L2 caches of a chip multiprocessor (CMP) for latency-oriented multithreaded appl...