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FCCM
2009
IEEE
148views VLSI» more  FCCM 2009»
14 years 3 months ago
A Packet Generator on the NetFPGA Platform
— A packet generator and network traffic capture system has been implemented on the NetFPGA. The NetFPGA is an open networking platform accelerator that enables rapid developmen...
G. Adam Covington, Glen Gibb, John W. Lockwood, Ni...
FCCM
2009
IEEE
165views VLSI» more  FCCM 2009»
14 years 3 months ago
Accelerating Quadrature Methods for Option Valuation
This paper presents an architecture for FPGA acceleration of quadrature methods used for pricing complex options, such as discrete barrier, Bermudan, and American options. The arc...
Anson H. T. Tse, David B. Thomas, Wayne Luk
FCCM
2009
IEEE
172views VLSI» more  FCCM 2009»
14 years 3 months ago
Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization
Abstract—Precision analysis and optimization is very important when transforming a floating-point algorithm into fixedpoint hardware implementations. The core analysis techniqu...
Jason Cong, Karthik Gururaj, Bin Liu, Chunyue Liu,...
DSN
2009
IEEE
14 years 3 months ago
Decoupling Dynamic Information Flow Tracking with a dedicated coprocessor
Dynamic Information Flow Tracking (DIFT) is a promising security technique. With hardware support, DIFT prevents a wide range of attacks on vulnerable software with minimal perfor...
Hari Kannan, Michael Dalton, Christos Kozyrakis
DSD
2009
IEEE
118views Hardware» more  DSD 2009»
14 years 3 months ago
Internet-Router Buffered Crossbars Based on Networks on Chip
—The scalability and performance of the Internet depends critically on the performance of its packet switches. Current packet switches are based on single-hop crossbar fabrics, w...
Kees Goossens, Lotfi Mhamdi, Iria Varela Senin
DSD
2009
IEEE
105views Hardware» more  DSD 2009»
14 years 3 months ago
Design of a Highly Dependable Beamforming Chip
—As CMOS process technology advances towards 32nm, SoC complexity continuously grows but its dependability significantly decreases. In this paper, a beamforming chip 1 is designe...
Xiao Zhang, Hans G. Kerkhoff
DSD
2009
IEEE
148views Hardware» more  DSD 2009»
14 years 3 months ago
SIMD Architectural Enhancements to Improve the Performance of the 2D Discrete Wavelet Transform
—The 2D Discrete Wavelet Transform (DWT) is a time-consuming kernel in many multimedia applications such as JPEG2000 and MPEG-4. The 2D DWT consists of horizontal filtering alon...
Asadollah Shahbahrami, Ben H. H. Juurlink
DSD
2009
IEEE
145views Hardware» more  DSD 2009»
14 years 3 months ago
High Performance Image Processing on a Massively Parallel Processor Array
Multicore and manycore processors are the new wave of computing, offering high performance by using large numbers of simple processors. In this paper, we describe the implementati...
Roberto R. Osorio, Cesar Diaz-Resco, Javier D. Bru...
DSD
2009
IEEE
118views Hardware» more  DSD 2009»
14 years 3 months ago
The Case for a Balanced Decomposition Process
—We present experiments with synthesis tools using examples which are currently believed to be very hard, namely the LEKU examples by Cong and Minkovich and parity examples of ou...
Jan Schmidt, Petr Fiser