DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
— During volume testing, test application time, test data volume and high performance automatic test equipment (ATE) are the major cost factors. Embedded testing including builti...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
Abstract—Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based ...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
—During post-silicon processor debugging, we need to frequently capture and dump out the internal state of the processor. Since internal state constitutes all memory elements, th...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
Abstract—To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
- Parallel architectures have become an increasingly popular method in which to achieve high performance with low power consumption. In order to leverage these benefits, applicatio...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
RTOS Simulation Henning Zabel, Wolfgang Mueller Universität Paderborn, C-LAB Fürstenallee 11, D-33102 Paderborn, Germany —Today, mobile and embedded real-time systems have to c...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
—Due to increasing complexity of design interactions between the chip, package and PCB, it is essential to consider them at the same time. Specifically the finger/pad locations...