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DDECS
2009
IEEE
128views Hardware» more  DDECS 2009»
14 years 3 months ago
A fast untestability proof for SAT-based ATPG
—Automatic Test Pattern Generation (ATPG) based on Boolean satisfiability (SAT) has been shown to be a beneficial complement to traditional ATPG techniques. Boolean solvers wor...
Daniel Tille, Rolf Drechsler
DDECS
2009
IEEE
111views Hardware» more  DDECS 2009»
14 years 3 months ago
0.5V 160-MHz 260uW all digital phase-locked loop
– A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and...
Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hs...
DDECS
2009
IEEE
106views Hardware» more  DDECS 2009»
14 years 3 months ago
Forward and backward guarding in early output logic
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...
Charlie Brej, Doug Edwards
DDECS
2009
IEEE
171views Hardware» more  DDECS 2009»
14 years 3 months ago
Packet header analysis and field extraction for multigigabit networks
—Packet header analysis and extraction of header fields needs to be performed in all network devices. As network speed is increasing quickly, high speed packet header processing...
Petr Kobierský, Jan Korenek, Libor Polcak
DATE
2009
IEEE
120views Hardware» more  DATE 2009»
14 years 3 months ago
Optimizing data flow graphs to minimize hardware implementation
Abstract - This paper describes an efficient graphbased method to optimize data-flow expressions for best hardware implementation. The method is based on factorization, common su...
Daniel Gomez-Prado, Q. Ren, Maciej J. Ciesielski, ...
DATE
2009
IEEE
129views Hardware» more  DATE 2009»
14 years 3 months ago
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network
Multi-domain clock skew scheduling is a cost effective technique for performance improvement. However, the required wire length and area overhead due to phase shifters for realizin...
Naser MohammadZadeh, Minoo Mirsaeedi, Ali Jahanian...
DATE
2009
IEEE
148views Hardware» more  DATE 2009»
14 years 3 months ago
Visual quality analysis for dynamic backlight scaling in LCD systems
—With the trend toward high-quality large form factor displays on high-end handhelds, LCD backlight accounts for a significant and increasing percentage of the total energy budg...
Andrea Bartolini, Martino Ruggiero, Luca Benini
DATE
2009
IEEE
149views Hardware» more  DATE 2009»
14 years 3 months ago
An ILP formulation for task mapping and scheduling on multi-core architectures
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tugh...
DATE
2009
IEEE
89views Hardware» more  DATE 2009»
14 years 3 months ago
Exploiting clock skew scheduling for FPGA
- Clock skew scheduling (CSS) is an effective technique to optimize clock period of sequential designs. However, these techniques are not effective in the presence of certain desig...
Sungmin Bae, Prasanth Mangalagiri, Narayanan Vijay...
DATE
2009
IEEE
126views Hardware» more  DATE 2009»
14 years 3 months ago
On hierarchical statistical static timing analysis
— Statistical static timing analysis deals with the increasing variations in manufacturing processes to reduce the pessimism in the worst case timing analysis. Because of the cor...
Bing Li, Ning Chen, Manuel Schmidt, Walter Schneid...