DSD
2009
IEEE
14 years 3 months ago
2009
IEEE
Feature sizes in VLSI circuits are steadily shrinking. This results in increasing susceptibility to soft errors, e.g. due to environmental radiation. Precautions against soft error...
DFT
2009
IEEE
14 years 3 months ago
2009
IEEE
Recently, a new test point insertion method for pseudo-random built-in self-test (BIST) was proposed in [Yang 09] which tries to use functional flip-flops to drive control test po...
DFT
2009
IEEE
14 years 3 months ago
2009
IEEE
This paper presents the first implementation of Built-In Self-Test (BIST) of Field Programmable Gate Arrays (FPGAs) using a soft core embedded processor for reconfiguration of the...
DFT
2009
IEEE
14 years 3 months ago
2009
IEEE
Hybrid CMOS/non-CMOS memories, in short hybrid memories, have been lauded as future ultra-capacity data memories. Nonetheless, such memories are going to suffer from high degree o...
DFT
2009
IEEE
14 years 3 months ago
2009
IEEE
We propose a framework that allows dual-layer cooperative error control in a nanoscale network-on-chip (NoC), to simultaneously improve reliability, performance and energy efficie...
DFT
2009
IEEE
14 years 3 months ago
2009
IEEE
The temperature dependence of MOSFET drain current varies with supply voltage. Two distinct voltage regions exist—a normal dependence (ND) region where an increase in temperatur...
DFT
2009
IEEE
14 years 3 months ago
2009
IEEE
This paper presents a study of errors that occur in DNA self-assembly using synthesized tile sets for template manufacturing. It is shown that due to the reduced size, aggregates ...
DFT
2009
IEEE
14 years 3 months ago
2009
IEEE
Pre-fabrication design verification and post-fabrication chip testing are two important stages in the product realization process. These two stages consume a large part of resourc...
DDECS
2009
IEEE
14 years 3 months ago
2009
IEEE
—Self-timed full adder designs based on commercial synchronous resources (standard cells), constructed using a mix of complete delay-insensitive codes adopted for inputs are desc...
DDECS
2009
IEEE
14 years 3 months ago
2009
IEEE
— We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints....