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DATE
2009
IEEE
94views Hardware» more  DATE 2009»
14 years 3 months ago
Improving compressed test pattern generation for multiple scan chain failure diagnosis
To reduce test data volumes, encoded tests and compacted test responses are widely used in industry. Use of test response compaction negatively impacts fault diagnosis since the e...
Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. ...
DATE
2009
IEEE
107views Hardware» more  DATE 2009»
14 years 3 months ago
Learning early-stage platform dimensioning from late-stage timing verification
— Today's innovations in the automotive sector are, to a great extent, based on electronics. The increasing integration complexity and stringent cost reduction goals turn E/...
Kai Richter, Marek Jersak, Rolf Ernst
DATE
2009
IEEE
138views Hardware» more  DATE 2009»
14 years 3 months ago
Scalable Adaptive Scan (SAS)
Scan compression has emerged as the most successful solution to solve the problem of rising manufacturing test cost. Compression technology is not hierarchical in nature. Hierarch...
Anshuman Chandra, Rohit Kapur, Yasunari Kanzawa
DATE
2009
IEEE
83views Hardware» more  DATE 2009»
14 years 3 months ago
Design optimizations to improve placeability of partial reconfiguration modules
Markus Koester, Wayne Luk, Jens Hagemeyer, Mario P...
DATE
2009
IEEE
86views Hardware» more  DATE 2009»
14 years 3 months ago
An efficient decoupling capacitance optimization using piecewise polynomial models
Xiaoyi Wang, Yici Cai, Sheldon X.-D. Tan, Xianlong...
DATE
2009
IEEE
129views Hardware» more  DATE 2009»
14 years 3 months ago
Exploring parallelizations of applications for MPSoC platforms using MPA
—This paper presents a tool for exploring different parallelization options for an application. It can be used to quickly find a high-quality match between an application and a ...
Rogier Baert, Erik Brockmeyer, Sven Wuytack, Thoma...
DATE
2009
IEEE
133views Hardware» more  DATE 2009»
14 years 3 months ago
SecBus: Operating System controlled hierarchical page-based memory bus protection
—This paper presents a new two-levels page-based memory bus protection scheme. A trusted Operating System drives a hardware cryptographic unit and manages security contexts for e...
Lifeng Su, Stephan Courcambeck, Pierre Guillemin, ...
DATE
2009
IEEE
119views Hardware» more  DATE 2009»
14 years 3 months ago
Statistical fault injection: Quantified error and confidence
— Fault injection has become a very classical method to determine the dependability of an integrated system with respect to soft errors. Due to the huge number of possible error ...
Régis Leveugle, A. Calvez, Paolo Maistri, P...
DATE
2009
IEEE
88views Hardware» more  DATE 2009»
14 years 3 months ago
Rewiring using IRredundancy Removal and Addition
—Redundancy Addition and Removal (RAR) is a restructuring technique used in the synthesis and optimization of logic designs. It can remove an existing target wire and add an alte...
Chun-Chi Lin, Chun-Yao Wang
DATE
2009
IEEE
113views Hardware» more  DATE 2009»
14 years 3 months ago
Incorporating graceful degradation into embedded system design
In this work, the focus is put on the behavior of a system in case a fault occurs that disables the system from executing its applications. Instead of executing a random subset of...
Michael Glaß, Martin Lukasiewycz, Christian ...