DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
Abstract—This work proposes reliability aware through silicon via (TSV) planning for the 3D stacked silicon integrated circuits (ICs). The 3D power distribution network is modele...
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
Abstract—Caches often employ write-back instead of writethrough, since write-back avoids unnecessary transfers for multiple writes to the same block. For several reasons, however...
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
Violations in memory references cause tremendous loss of productivity, catastrophic mission failures, loss of privacy and security, and much more. Software mechanisms to detect me...
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
—Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay ...
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
There is a growing concern about timing errors resulting from design marginalities and the effects of circuit aging on speed-paths in logic circuits. This paper presents a low ove...
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
—Complex signal processing algorithms are often specified in floating point precision. Thus, a type conversion is needed when the targeted platform requires fixed-point precis...
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
Recently proposed techniques for peak power management [5] involve centralized decision-making and assume quick evaluation of the various power management states. These techniques...
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
Abstract—The generation of device drivers is a very time consuming and error prone activity. All the strategies proposed up to now to simplify this operation require a manual, ev...
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
—In this paper, we propose a novel on-chip communication scheme by dividing the resources of a traditional packet-switched network-on-chip between a packet-switched and a circuit...