DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
In modern digital ICs, the increasing demand for performance and throughput requires operating frequencies of hundreds of megahertz, and in several cases exceeding the gigahertz r...
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
—It is generally acknowledged that nanoelectronics will eventually replace traditional silicon CMOS in high-performance integrated circuits. To that end, considerable investments...
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
— Modern processors are becoming more complex and as features and application size increase, their evaluation is becoming more time-consuming. To date, design space exploration r...
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
—We present an optimal methodology for dynamic voltage scheduling problem in the presence of realistic assumption such as leakage-power and intra-task overheads. Our contribution...
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
Abstract— In many current SoCs, the architectural interface to onchip monitors is ad hoc and inefficient. In this paper, a new architectural approach which advocates the use of a...
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
The Active Buffer project is part of the CBM (compressed baryonic matter) experiment and takes advantage of the DPR (dynamic partial reconfiguration) technology, in which a dynam...
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
— As clock frequencies exceed giga-Hertz, the extra power loss due to conductor surface roughness in interconnects and packagings is more evident and thus demands a proper accou...
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
this paper proposes a novel Process Variation Aware SRAM architecture designed to inherently support voltage scaling. The peripheral circuitry of the SRAM is modified to selectivel...