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DATE
2009
IEEE
92views Hardware» more  DATE 2009»
14 years 4 months ago
Using randomization to cope with circuit uncertainty
—Future computing systems will feature many cores that run fast, but might show more faults compared to existing CMOS technologies. New software methodologies must be adopted to ...
Hamid Safizadeh, Mohammad Tahghighi, Ehsan K. Arde...
DATE
2009
IEEE
123views Hardware» more  DATE 2009»
14 years 4 months ago
Shock immunity enhancement via resonance damping in gyroscopes for automotive applications
—This paper presents an innovative and effective method to improve the performance of a micro mechanical gyroscope by introducing the damping of its sensing quality factor. Indee...
Eleonora Marchetti, Luca Fanucci, A. Rocchi, Marco...
DATE
2009
IEEE
136views Hardware» more  DATE 2009»
14 years 4 months ago
A file-system-aware FTL design for flash-memory storage systems
Abstract—As flash memory became popular over various platforms, there is a strong demand on the performance degradation problem, due to the special characteristics of flash mem...
Po-Liang Wu, Yuan-Hao Chang, Tei-Wei Kuo
DATE
2009
IEEE
88views Hardware» more  DATE 2009»
14 years 4 months ago
Latency criticality aware on-chip communication
—Packet-switched interconnect fabric is a promising on-chip communication solution for many-core architectures. It offers high throughput and excellent scalability for on-chip da...
Zheng Li, Jie Wu, Li Shang, Robert P. Dick, Yihe S...
DATE
2009
IEEE
110views Hardware» more  DATE 2009»
14 years 4 months ago
Trace signal selection for visibility enhancement in post-silicon validation
Today’s complex integrated circuit designs increasingly rely on post-silicon validation to eliminate bugs that escape from presilicon verification. One effective silicon debug ...
Xiao Liu, Qiang Xu
DATE
2009
IEEE
76views Hardware» more  DATE 2009»
14 years 4 months ago
Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture
Sean Whitty, Henning Sahlbach, Rolf Ernst, Wolfram...
DATE
2009
IEEE
119views Hardware» more  DATE 2009»
14 years 4 months ago
On-chip communication architecture exploration for processor-pool-based MPSoC
— MPSoC is evolving towards processor-pool (PP)-based architectures, which employ hierarchical on-chip network for inter- and intra-PP communication. Since the design space of PP...
Young-Pyo Joo, Sungchan Kim, Soonhoi Ha
DATE
2009
IEEE
145views Hardware» more  DATE 2009»
14 years 4 months ago
Joint logic restructuring and pin reordering against NBTI-induced performance degradation
Negative Bias Temperature Instability (NBTI), a PMOS aging phenomenon causing significant loss on circuit performance and lifetime, has become a critical challenge for temporal re...
Kai-Chiang Wu, Diana Marculescu
DATE
2009
IEEE
135views Hardware» more  DATE 2009»
14 years 4 months ago
Gate replacement techniques for simultaneous leakage and aging optimization
—1As technology scales, the aging effect caused by Negative Bias Temperature Instability (NBTI) has become a major reliability concern for circuit designers. On the other hand, r...
Yu Wang 0002, Xiaoming Chen, Wenping Wang, Yu Cao,...
DATE
2009
IEEE
133views Hardware» more  DATE 2009»
14 years 4 months ago
Pipelined data parallel task mapping/scheduling technique for MPSoC
—In this paper, we propose a multi-task mapping/scheduling technique for heterogeneous and scalable MPSoC. To utilize the large number of cores embedded in MPSoC, the proposed te...
Hoeseok Yang, Soonhoi Ha