Leakage energy will be the major energy consumer in future deep sub-micron designs. Especially the memory sub-system of future SOCs will be negatively affected by this trend. In o...
DNA probe arrays have emerged as a core genomic technology that enables cost-effective gene expression monitoring, mutation detection, single nucleotide polymorphism analysis and ...
Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu ...
: Adaptive transceivers can significantly reduce the energy consumption of a mobile, battery-powered node by capturing realtime changes in the communication channel. This paper pro...
— Memory-intensive applications present unique challenges to an ASIC designer in terms of the choice of memory organization, memory size requirements, bandwidth and access latenc...
Dynamic voltage scaling (DVS) is arguably the most effective energy reduction technique. The multiple-voltage DVS systems, which can operate only at pre-determined discrete voltag...
In this paper, we propose a novel framework for fast multilevel routing considering crosstalk and performance optimization. To handle the crosstalk minimization problem, we incorp...
Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Le...
This paper proposes a scheme that captures diverse input waveforms of CMOS gates for static timing analysis. Conventionally the latest arrival time and transition time are calcula...
— In this paper, we present a high-level power model to estimate the power consumption in semi-global and global interconnects. Such interconnects are used for communications bet...
Path delay fault testing becomes increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay...
Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Pun...