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ICCD
2000
IEEE
116views Hardware» more  ICCD 2000»
14 years 6 months ago
Representing and Scheduling Looping Behavior Symbolically
This paper presents a very general, exact technique for scheduling looping data-flow graphs. In contrast to the conventional technique using loop iteration variables and integer ...
Steve Haynal, Forrest Brewer
ICCD
2000
IEEE
93views Hardware» more  ICCD 2000»
14 years 6 months ago
Cheap Out-of-Order Execution Using Delayed Issue
In superscalar architectures, out-of-order issue mechanisms increase performance by dynamically rescheduling instructions that cannot be statically reordered by the compiler. Whil...
J. P. Grossman
ICCD
2000
IEEE
135views Hardware» more  ICCD 2000»
14 years 6 months ago
A Methodology and Tool for Automated Transformational High-Level Design Space Exploration
el of abstraction by integrating a high-level estimation step. This results in a design loop which is tight led on high level of abstraction (called estimation loop in figure 1). ...
Joachim Gerlach, Wolfgang Rosenstiel
ICCD
2000
IEEE
125views Hardware» more  ICCD 2000»
14 years 6 months ago
Architectural Support for Dynamic Memory Management
Recent advances in software engineering, such as graphical user intevaces and object-oriented programming, have caused applications to become more memory intensive. These applicat...
J. Morris Chang, Witawas Srisa-an, Chia-Tien Dan L...
ICCD
2000
IEEE
103views Hardware» more  ICCD 2000»
14 years 6 months ago
Efficient Place and Route for Pipeline Reconfigurable Architectures
In this paper, we present a fast and eficient compilation methodology for pipeline reconfigurable architectures. Our compiler back-end is much faster than conventional CAD tools, ...
Srihari Cadambi, Seth Copen Goldstein
ICCD
2000
IEEE
75views Hardware» more  ICCD 2000»
14 years 6 months ago
Hybridizing and Coalescing Load Value Predictors
Most well-performing load value predictors are hybrids that combine multiple predictors into one. Such hybrids are often large. To reduce their size and to improve their performan...
Martin Burtscher, Benjamin G. Zorn
ICCD
2001
IEEE
119views Hardware» more  ICCD 2001»
14 years 6 months ago
A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage
We present a simulation-based semi-formal verification method for sequential circuits described at the registertransfer level. The method consists of an iterative loop where cove...
Serdar Tasiran, Farzan Fallah, David G. Chinnery, ...
ICCD
2001
IEEE
120views Hardware» more  ICCD 2001»
14 years 6 months ago
Design of a Predictive Filter Cache for Energy Savings in High Performance Processor Architectures
Filter cache has been proposed as an energy saving architectural feature [9]. A filter cache is placed between the CPU and the instruction cache (I-cache) to provide the instruct...
Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau
ICCD
2001
IEEE
114views Hardware» more  ICCD 2001»
14 years 6 months ago
Allocation by Conflict: A Simple Effective Multilateral Cache Management Scheme
Several schemes have been proposed that incorporate an auxiliary buffer to improve the performance of a given size cache. Victim caching, aims to reduce the impact of conflict mis...
Edward S. Tam, Stevan A. Vlaovic, Gary S. Tyson, E...