ICCD
2001
IEEE
14 years 9 months ago
2001
IEEE
CMOS Phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper...
ICCD
2001
IEEE
14 years 9 months ago
2001
IEEE
Abstract-- Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 2GHz has caused crosstalk noise to become a serious problem, that degr...
ICCD
2001
IEEE
14 years 9 months ago
2001
IEEE
This paper introduces minimal subset evaluation (MSE) as a way to reduce time spent on large-structure warm-up during the fastforwarding portion of processor simulations. Warm up ...
ICCD
2001
IEEE
14 years 9 months ago
2001
IEEE
Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of increased static energy consumption ...
ICCD
2001
IEEE
14 years 9 months ago
2001
IEEE
ICCD
2001
IEEE
14 years 9 months ago
2001
IEEE
Lowering power consumption in microprocessors, whether used in portables or not, has now become one of the most critical design concerns. On-chip cache memories tend to occupy dom...
ICCD
2001
IEEE
14 years 9 months ago
2001
IEEE
As the operating frequency increases to Giga Hertz and the rise time of a signal is less than or comparable to the time-of-flight delay of a line, it is necessary to consider the...
ICCD
2001
IEEE
14 years 9 months ago
2001
IEEE
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...
ICCD
2001
IEEE
14 years 9 months ago
2001
IEEE
ICCD
2001
IEEE
14 years 9 months ago
2001
IEEE
‡ Physical and generic models that analytically couple the array architecture of CMOS SRAMs with the wire lengths and fan-outs along critical paths to decode and sense data are r...