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ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
14 years 9 months ago
An Accurate Combinatorial Model for Performance Prediction of Deterministic Wormhole Routing in Torus Multicomputer Systems
Although several analytical models have been proposed in the literature for different interconnection networks with deterministic routing, very few of them have considered the eff...
Hashem Hashemi Najaf-abadi, Hamid Sarbazi-Azad
ICCD
2004
IEEE
106views Hardware» more  ICCD 2004»
14 years 9 months ago
A New Statistical Optimization Algorithm for Gate Sizing
— In this paper, we approach the gate sizing problem in VLSI circuits in the context of increasing variability of process and circuit parameters as technology scales into the nan...
Murari Mani, Michael Orshansky
ICCD
2004
IEEE
125views Hardware» more  ICCD 2004»
14 years 9 months ago
IPC Driven Dynamic Associative Cache Architecture for Low Energy
Existing schemes for cache energy optimization incorporate a limited degree of dynamic associativity: either direct mapped or full available associativity (say 4-way). In this pap...
Sriram Nadathur, Akhilesh Tyagi
ICCD
2004
IEEE
74views Hardware» more  ICCD 2004»
14 years 9 months ago
Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2
In this paper we present a clustered, multiple-clock domain (CMCD) microarchitecture that combines the benefits of both clustering and Globally Asynchronous Locally Synchronous (G...
Grigorios Magklis, José González, An...
ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
14 years 9 months ago
Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems
Three dimensional vertically integrated systems allow active devices to be placed on multiple device layers. In recent years, a number of research efforts have addressed physical ...
Madhubanti Mukherjee, Ranga Vemuri
ICCD
2004
IEEE
107views Hardware» more  ICCD 2004»
14 years 9 months ago
Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor
In this work we propose a methodology for the accurate analysis of the power consumption of interprocessor communication in a MPSoC, and the construction of high-level power macro...
Mirko Loghi, Luca Benini, Massimo Poncino
ICCD
2004
IEEE
99views Hardware» more  ICCD 2004»
14 years 9 months ago
An Efficient Algorithm for Reconfiguring Shared Spare RRAM
Redundant rows and columns have been used for years to improve the yield of DRAM fabrication. However, finding a memory repair solution has been proved to be an NP-complete proble...
Hung-Yau Lin, Hong-Zu Chou, Fu-Min Yeh, Ing-Yi Che...
ICCD
2004
IEEE
96views Hardware» more  ICCD 2004»
14 years 9 months ago
Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study
Dynamic address compression schemes that exploit address locality can help reduce both address bus energy and cost simultaneously with only a small performance penalty. In this wo...
Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Maha...
ICCD
2004
IEEE
120views Hardware» more  ICCD 2004»
14 years 9 months ago
XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs
This paper describes XTalkDelay, an industrial-strength methodology and tool for measuring the impact of crosstalk on delays of paths in a design. The main cornerstone of XTalkDel...
Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwin...
ICCD
2004
IEEE
109views Hardware» more  ICCD 2004»
14 years 9 months ago
Low Power Test Data Compression Based on LFSR Reseeding
Many test data compression schemes are based on LFSR reseeding. A drawback of these schemes is that the unspecified bits are filled with random values resulting in a large number ...
Jinkyu Lee, Nur A. Touba