Sciweavers

ICCD
2004
IEEE
97views Hardware» more  ICCD 2004»
14 years 9 months ago
A General Post-Processing Approach to Leakage Current Reduction in SRAM-Based FPGAs
A negative effect of ever-shrinking supply and threshold voltages is the larger percentage of total power consumption that comes from leakage current. Several techniques have been...
John Lach, Jason Brandon, Kevin Skadron
ICCD
2004
IEEE
149views Hardware» more  ICCD 2004»
14 years 9 months ago
Adaptive Selection of an Index in a Texture Cache
For a specified application, there is an opportunity to improve cache performance by smart choosing of index bits of a cache. A texture cache for texture mapping of 3D computer gr...
Chun-Ho Kim, Lee-Sup Kim
ICCD
2004
IEEE
126views Hardware» more  ICCD 2004»
14 years 9 months ago
Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling
Simultaneous Multithreading (SMT) is emerging as an effective microarchitecture model to increase the utilization of resources in modern super-scalar processors. However, co-sched...
Joshua L. Kihm, Daniel A. Connors
ICCD
2004
IEEE
91views Hardware» more  ICCD 2004»
14 years 9 months ago
FPGA Emulation of Quantum Circuits
Ahmed Usman Khalid, Zeljko Zilic, Katarzyna Radeck...
ICCD
2004
IEEE
154views Hardware» more  ICCD 2004»
14 years 9 months ago
A High-Frequency Decimal Multiplier
Decimal arithmetic is regaining popularity in the computing community due to the growing importance of commercial, financial, and Internet-based applications, which process decima...
Robert D. Kenney, Michael J. Schulte, Mark A. Erle
ICCD
2004
IEEE
98views Hardware» more  ICCD 2004»
14 years 9 months ago
Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture
Networks-on-Chip (NoC), a new SoC paradigm, has been proposed as a solution to mitigate complex on-chip interconnect problems. NoC architecture consists of a collection of IP core...
Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharide...
ICCD
2004
IEEE
112views Hardware» more  ICCD 2004»
14 years 9 months ago
An Infrastructure IP for On-Chip Clock Jitter Measurement
In this paper, we present an infrastructure IP core to facilitate on-chip clock jitter measurement. In the proposed approach, the clock signal under test is delayed by two differe...
Jui-Jer Huang, Jiun-Lang Huang
ICCD
2004
IEEE
112views Hardware» more  ICCD 2004»
14 years 9 months ago
Combined Channel Segmentation and Buffer Insertion for Routability and Performance Improvement of Field
In this paper, we propose a combined channel segmentation and buffer insertion approach, which minimizes the number of buffers inserted while satisfying the delay constraints for ...
Hu Huang, Joseph B. Bernstein, Martin Peckerar, Ji...