ICCD
2004
IEEE
14 years 9 months ago
2004
IEEE
Abstract— This paper proposes a technique for creating a combinational logic network with an output that signals when all other outputs have stabilized. The method is based on du...
ICCD
2004
IEEE
14 years 9 months ago
2004
IEEE
ICCD
2004
IEEE
14 years 9 months ago
2004
IEEE
In many workloads, 25% to 50% of instructions have slack allowing them to be delayed without impacting performance. To exploit this slack, processors may implement more power-efï¬...
ICCD
2004
IEEE
14 years 9 months ago
2004
IEEE
I/O placement has always been a concern in modern IC design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the...
ICCD
2004
IEEE
14 years 9 months ago
2004
IEEE
As frequencies and feature size scale faster than operating voltages, power density is increasing in each processor generation. Power density and the cost of removing the heat it ...
ICCD
2004
IEEE
2004
IEEE
Circuit-Based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation
14 years 9 months ago
In this paper we discuss the application of circuit-based logical reasoning to simplify optimization problems expressed as integer linear programs (ILP) over circuit states. We de...
ICCD
2004
IEEE
14 years 9 months ago
2004
IEEE
Wire pipelining has been proposed as a viable mean to break the discrepancy between decreasing gate delays and increasing wire delays in deep-submicron technologies. Far from bein...
ICCD
2004
IEEE
14 years 9 months ago
2004
IEEE
This paper shows that by creating functional scan chains at the register-transfer level (RTL), not only the timing of the circuit can be improved, but also the test data compressi...
ICCD
2004
IEEE
14 years 9 months ago
2004
IEEE
Although scan-based designs are widely used in order to reduce the complexity of test generation, test application time and test data volume are substantially increased. We propos...
ICCD
2004
IEEE
14 years 9 months ago
2004
IEEE
This short paper explores an implementation of a new technology called 3D die stacking and describes research activity at Intel. 3D die stacking is the bonding of two die either f...