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ISLPED
2007
ACM
97views Hardware» more  ISLPED 2007»
13 years 10 months ago
Detailed placement for leakage reduction using systematic through-pitch variation
We present a novel detailed placement technique that accounts for systematic through-pitch variations to reduce leakage. Leakage depends nearly exponentially on linewidth (gate le...
Andrew B. Kahng, Swamy Muddu, Puneet Sharma
ASAP
2010
IEEE
193views Hardware» more  ASAP 2010»
13 years 10 months ago
Automatic generation of polynomial-based hardware architectures for function evaluation
Abstract--Polynomial approximation is a very general technique for the evaluation of a wide class of numerical functions of one variable. This article details an architecture gener...
Florent de Dinechin, Mioara Joldes, Bogdan Pasca
ASAP
2010
IEEE
138views Hardware» more  ASAP 2010»
13 years 10 months ago
Enhancing performance of network-on-chip architectures with millimeter-wave wireless interconnects
In a traditional Network-on-Chip (NoC), latency and power dissipation increase with system size due to its inherent multi-hop communications. The performance of NoC communication ...
Sujay Deb, Amlan Ganguly, Kevin Chang, Partha Prat...
ISLPED
2007
ACM
92views Hardware» more  ISLPED 2007»
13 years 10 months ago
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI
Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) ...
Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh
FPL
2008
Springer
138views Hardware» more  FPL 2008»
13 years 10 months ago
An efficient run-time router for connecting modules in FPGAS
It is often desirable to change the logic and/or the connections within an FPGA design on-the-fly without the benefit of a workstation or vendor CAD software. This paper presents ...
Jorge Surís, Cameron Patterson, Peter Athan...
ASAP
2010
IEEE
142views Hardware» more  ASAP 2010»
13 years 10 months ago
Implementing decimal floating-point arithmetic through binary: Some suggestions
We propose several algorithms and provide some related results that make it possible to implement decimal floating-point arithmetic on a processor that does not have decimal opera...
Nicolas Brisebarre, Nicolas Louvet, Érik Ma...
FPL
2008
Springer
112views Hardware» more  FPL 2008»
13 years 10 months ago
Fault tolerant methods for reliability in FPGAs
Reliability and process variability are serious issues for FPGAs in the future. Fortunately FPGAs have the ability to reconfigure in the field and at runtime, thus providing oppor...
Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheu...
ASAP
2010
IEEE
128views Hardware» more  ASAP 2010»
13 years 10 months ago
An optimized NoC architecture for accelerating TSP kernels in breakpoint median problem
Turbo Majumder, Souradip Sarkar, Partha Pande, Ana...
ASAP
2010
IEEE
127views Hardware» more  ASAP 2010»
13 years 10 months ago
Deadlock-avoidance for streaming applications with split-join structure: Two case studies
Peng Li, Kunal Agrawal, Jeremy Buhler, Roger D. Ch...
FPL
2008
Springer
207views Hardware» more  FPL 2008»
13 years 10 months ago
Bitstream compression techniques for Virtex 4 FPGAs
This paper examines the opportunity of using compression for accelerating the (re)configuration of FPGA devices, focusing on the choice of compression algorithms, and their hardwa...
Radu Stefan, Sorin Dan Cotofana