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ISLPED
2007
ACM
84views Hardware» more  ISLPED 2007»
13 years 10 months ago
Towards a software approach to mitigate voltage emergencies
Increases in peak current draw and reductions in the operating voltages of processors continue to amplify the importance of dealing with voltage fluctuations in processors. One a...
Meeta Sharma Gupta, Krishna K. Rangan, Michael D. ...
FPL
2008
Springer
96views Hardware» more  FPL 2008»
13 years 10 months ago
Towards benchmarking energy efficiency of reconfigurable architectures
Energy research in reconfigurable architectures often involves legacy benchmarks such as the MCNC benchmarks. These benchmarks, however, are not well-suited for assessing energy c...
Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y....
ISLPED
2007
ACM
132views Hardware» more  ISLPED 2007»
13 years 10 months ago
Thermal response to DVFS: analysis with an Intel Pentium M
Increasing power density in computing systems from laptops to servers has spurred interest in dynamic thermal management. Based on the success of dynamic voltage and frequency sca...
Heather Hanson, Stephen W. Keckler, Soraya Ghiasi,...
ASAP
2010
IEEE
127views Hardware» more  ASAP 2010»
13 years 10 months ago
Design of throughput-optimized arrays from recurrence abstractions
urrence abstractions Arpith C. Jacob Jeremy D. Buhler Roger D. Chamberlain Arpith C. Jacob, Jeremy D. Buhler, and Roger D. Chamberlain, "Design of ut-optimized arrays from rec...
Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chambe...
FPL
2008
Springer
141views Hardware» more  FPL 2008»
13 years 10 months ago
An analytical model describing the relationships between logic architecture and FPGA density
This paper describes an analytical model, based principally on Rent's Rule, that relates logic architectural parameters to the area efficiency of an FPGA. In particular, the ...
Andrew Lam, Steven J. E. Wilton, Philip Heng Wai L...
ISLPED
2007
ACM
94views Hardware» more  ISLPED 2007»
13 years 10 months ago
Design of an efficient power delivery network in an soc to enable dynamic power management
Dynamic voltage scaling (DVS) is known to be one of the most efficient techniques for power reduction of integrated circuits. Efficient low voltage DC-DC conversion is a key enabl...
Behnam Amelifard, Massoud Pedram
FPL
2008
Springer
104views Hardware» more  FPL 2008»
13 years 10 months ago
A technique for minimizing power during FPGA placement
This paper considers the implementation of an annealing technique for dynamic power reduction in FPGAs. The proposed method comprises a power-aware objective function for placemen...
Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Ya...
FPL
2008
Springer
94views Hardware» more  FPL 2008»
13 years 10 months ago
Acceleration of a production rigid molecule docking code
: Modeling the interactions of biological molecules, or docking is critical to both understanding basic life processes and to designing new drugs. Here we describe the FPGA-based a...
Bharat Sukhwani, Martin C. Herbordt
FPL
2008
Springer
105views Hardware» more  FPL 2008»
13 years 10 months ago
Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems
A high-speed and secure dynamic partial reconfiguration (DPR) system is realized with AES-GCM that guarantees both confidentiality and authenticity of FPGA bitstreams. In DPR syst...
Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji T...
ISLPED
2007
ACM
110views Hardware» more  ISLPED 2007»
13 years 10 months ago
A 0.4-V UWB baseband processor
A 0.4-V UWB digital baseband processor has been fabricated in a standard-VT 90-nm CMOS technology. The baseband processor operates at an ultra-low supply voltage to reduce energy ...
Vivienne Sze, Anantha P. Chandrakasan