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ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
14 years 5 days ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha
ICCAD
1995
IEEE
170views Hardware» more  ICCAD 1995»
14 years 5 days ago
Acceleration techniques for dynamic vector compaction
: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly...
Anand Raghunathan, Srimat T. Chakradhar
ICCAD
1995
IEEE
90views Hardware» more  ICCAD 1995»
14 years 5 days ago
Design-for-debugging of application specific designs
Miodrag Potkonjak, Sujit Dey, Kazutoshi Wakabayash...
ICCAD
1995
IEEE
84views Hardware» more  ICCAD 1995»
14 years 5 days ago
Statistical behavioral modeling and characterization of A/D converters
This paper presents a method to characterize Nyquist rate A/D converters based on the use of a first order statistical behavioral model. The proposed model is derived from a very...
Eduardo J. Peralías, Adoración Rueda...
ICCAD
1995
IEEE
106views Hardware» more  ICCAD 1995»
14 years 5 days ago
Re-engineering of timing constrained placements for regular architectures
In a typical design ow, the design may be altered slightly several times after the initial design cycle according to minor changes in the design speci cation either as a result o...
Anmol Mathur, K. C. Chen, C. L. Liu
ICCAD
1995
IEEE
90views Hardware» more  ICCAD 1995»
14 years 5 days ago
An optimal algorithm for area minimization of slicing floorplans
The traditional algorithm of Stockmeyer for area minimization of slicing oorplans has time (and space) complexity O(n2 ) in the worst case, or O(nlogn) for balanced slicing. For ...
Weiping Shi
ICCAD
1995
IEEE
95views Hardware» more  ICCAD 1995»
14 years 5 days ago
A sequential quadratic programming approach to concurrent gate and wire sizing
With an ever-increasing portion of the delay in highspeed CMOS chips attributable to the interconnect, interconnect-circuit design automation continues to grow in importance. By t...
Noel Menezes, Ross Baldick, Lawrence T. Pileggi
ICCAD
1995
IEEE
92views Hardware» more  ICCAD 1995»
14 years 5 days ago
Linear decomposition algorithm for VLSI design applications
Jianmin Li, John Lillis, Chung-Kuan Cheng
ICCAD
1995
IEEE
180views Hardware» more  ICCAD 1995»
14 years 5 days ago
Design based analog testing by Characteristic Observation Inference
In this paper, a new approach to analog test design based on the circuit design process, called Characteristic Observation Inference (COI), is presented. In many situations, it is...
Walter M. Lindermeir, Helmut E. Graeb, Kurt Antrei...