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ICCAD
1995
IEEE
136views Hardware» more  ICCAD 1995»
14 years 5 days ago
A controller-based design-for-testability technique for controller-data path circuits
This paper investigates the effect of the controller on the testability of sequential circuits composed of controllers and data paths. It is shown that even when both the controll...
Sujit Dey, Vijay Gangaram, Miodrag Potkonjak
ICCAD
1995
IEEE
78views Hardware» more  ICCAD 1995»
14 years 5 days ago
A unified approach to topology generation and area optimization of general floorplans
Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab...
ICCAD
1995
IEEE
140views Hardware» more  ICCAD 1995»
14 years 5 days ago
Bounded-skew clock and Steiner routing under Elmore delay
: We study the minimum-cost bounded-skew routing tree problem under the Elmore delay model. We presenttwo approachesto construct bounded-skew routing trees: (i) the Boundary Mergin...
Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-...
ICCAD
1995
IEEE
127views Hardware» more  ICCAD 1995»
14 years 5 days ago
Hybrid decision diagrams
Abstract: Functions that map boolean vectors into the integers are important for the design and veri cation of arithmetic circuits. MTBDDs and BMDs have been proposed for represent...
Edmund M. Clarke, Masahiro Fujita, Xudong Zhao
ICCAD
1995
IEEE
97views Hardware» more  ICCAD 1995»
14 years 5 days ago
Interface co-synthesis techniques for embedded systems
A key aspect of the synthesis of embedded systems is the automatic integration of system components. This entails the derivation of both the hardware and software interfaces that ...
Pai H. Chou, Ross B. Ortega, Gaetano Borriello
ICCAD
1995
IEEE
67views Hardware» more  ICCAD 1995»
14 years 5 days ago
Fault emulation: a new approach to fault grading
Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai
ICCAD
1995
IEEE
163views Hardware» more  ICCAD 1995»
14 years 5 days ago
Signal integrity optimization on the pad assignment for high-speed VLSI design
Pad assignment with signal integrity optimization is very important for high-speed VLSI design. In this paper, an efficient method is proposed to effectively minimize both simulta...
Kai-Yuan Chao, D. F. Wong
ICCAD
1995
IEEE
88views Hardware» more  ICCAD 1995»
14 years 5 days ago
LOT: logic optimization with testability-new transformations using recursive learning
: A new approach to optimize multi-level logic circuits is introduced. Given a multi-level circuit, the synthesis method optimizes its area, simultaneously enhancing its random pat...
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang K...