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ICCAD
1995
IEEE
113views Hardware» more  ICCAD 1995»
14 years 5 days ago
Logic decomposition during technology mapping
—A problem in technology mapping is that the quality of the final implementation depends significantly on the initially provided circuit structure. This problem is critical, es...
Eric Lehman, Yosinori Watanabe, Joel Grodstein, He...
ICCAD
1995
IEEE
79views Hardware» more  ICCAD 1995»
14 years 5 days ago
Optimal wire sizing and buffer insertion for low power and a generalized delay model
John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin
ICCAD
1995
IEEE
108views Hardware» more  ICCAD 1995»
14 years 5 days ago
Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels
This paper presents a linear time algorithm to reduce a large RC interconnect network into subnetworks which are approximated with lower order equivalent RC circuits. The number o...
Haifang Liao, Wayne Wei-Ming Dai
ICCAD
1995
IEEE
167views Hardware» more  ICCAD 1995»
14 years 5 days ago
A novel methodology for statistical parameter extraction
IC manufacturing process variations are typically expressed in terms of joint probability density functions (jpdf’s) or as worst case combinations/corners of the device model pa...
Kannan Krishna, Stephen W. Director
ICCAD
1995
IEEE
68views Hardware» more  ICCAD 1995»
14 years 5 days ago
Generating sparse partial inductance matrices with guaranteed stability
This paper proposes a definition of magnetic vector potential that can be used to evaluate sparse partial inductance matrices. Unlike the commonly applied procedure of discarding...
Byron Krauter, Lawrence T. Pileggi
ICCAD
1995
IEEE
144views Hardware» more  ICCAD 1995»
14 years 5 days ago
Background memory management for dynamic data structure intensive processing systems
Abstract -- Telecommunication network management applications often require application-specific ICs that use large dynamically allocated stored data structures. Currently availab...
Gjalt G. de Jong, Bill Lin, Carl Verdonck, Sven Wu...
ICCAD
1995
IEEE
120views Hardware» more  ICCAD 1995»
14 years 5 days ago
Pattern generation for a deterministic BIST scheme
Recently a deterministic built-in self-test scheme has been presented based on reseeding of multiple-polynomial linear feedback shift registers. This scheme encodes deterministic ...
Sybille Hellebrand, Birgit Reeb, Steffen Tarnick, ...
ICCAD
1995
IEEE
134views Hardware» more  ICCAD 1995»
14 years 5 days ago
A delay model for logic synthesis of continuously-sized networks
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
Joel Grodstein, Eric Lehman, Heather Harkness, Bil...