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ASYNC
2004
IEEE
98views Hardware» more  ASYNC 2004»
14 years 13 days ago
Synthesis of Speed Independent Circuits Based on Decomposition
This paper presents a decomposition method for speedindependent circuit design that is capable of significantly reducing the cost of synthesis. In particular, this method synthesi...
Tomohiro Yoneda, Hiroomi Onda, Chris J. Myers
ASYNC
2004
IEEE
121views Hardware» more  ASYNC 2004»
14 years 13 days ago
Static Tokens: Using Dataflow to Automate Concurrent Pipeline Synthesis
We describe a new intermediate compiler representation, static token form, that is suitable for dataflow-style synthesis of high-level asynchronous specifications. Static token fo...
John Teifel, Rajit Manohar
ASYNC
2004
IEEE
78views Hardware» more  ASYNC 2004»
14 years 13 days ago
Hiding Synchronization Delays in a GALS Processor Microarchitecture
We analyze an Alpha 21264-like Globally
Greg Semeraro, David H. Albonesi, Grigorios Magkli...
ASYNC
2004
IEEE
133views Hardware» more  ASYNC 2004»
14 years 13 days ago
An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm
One of the main reasons for using asynchronous design is that it offers the opportunity to exploit the datadependent latency of many operations in order to achieve low-power, high...
Aristides Efthymiou, W. Suntiamorntut, Jim D. Gars...
ASYNC
2004
IEEE
107views Hardware» more  ASYNC 2004»
14 years 13 days ago
A Fast and Energy-Efficient Stack
We present some novel hardware implementations of a stack. All designs are clockless, fast, and energy efficient, while occupying modest area. We implemented a 42-place stack chip...
Jo C. Ebergen, Daniel Finchelstein, Russell Kao, J...
ASYNC
2004
IEEE
102views Hardware» more  ASYNC 2004»
14 years 13 days ago
Non-Uniform Access Asynchronous Register Files
Register files of microprocessors have often been cited as performance bottlenecks and significant consumers of energy. The robust and modular nature of quasi-delay insensitive (Q...
David Fang, Rajit Manohar
ASYNC
2004
IEEE
107views Hardware» more  ASYNC 2004»
14 years 13 days ago
Analog Micropipeline Rings for High Precision Timing
I use asynchronous FIFO stages that are connected in rings to generate and deliver highly precise timing signals. I introduce a Micropipeline FIFO control stage that oscillates at...
Scott Fairbanks, Simon W. Moore
ASYNC
2004
IEEE
90views Hardware» more  ASYNC 2004»
14 years 13 days ago
Handshake Protocols for De-Synchronization
De-synchronization appears as a new paradigm to automate the design of asynchronous circuits from synchronous netlists. This paper studies different protocols for de-synchronizatio...
Ivan Blunno, Jordi Cortadella, Alex Kondratyev, Lu...
ASYNC
2004
IEEE
61views Hardware» more  ASYNC 2004»
14 years 13 days ago
Long Wires and Asynchronous Control
As integrated circuit technologies get smaller, circuit and architectural trends make transmitting data across long on-chip wires increasingly important yet increasingly expensive...
Ron Ho, Jonathan Gainsley, Robert J. Drost
ASPDAC
2004
ACM
158views Hardware» more  ASPDAC 2004»
14 years 13 days ago
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...