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ASPDAC
2007
ACM
67views Hardware» more  ASPDAC 2007»
14 years 21 days ago
Synthesis of Reversible Sequential Elements
Min-Lun Chuang, Chun-Yao Wang
ASPDAC
2007
ACM
123views Hardware» more  ASPDAC 2007»
14 years 21 days ago
Creating Explicit Communication in SoC Models Using Interactive Re-Coding
Communication exploration has become a critical step during SoC design. Researchers in the CAD community have proposed fast and efficient techniques for comprehensive design space ...
Pramod Chandraiah, Junyu Peng, Rainer Dömer
ATVA
2009
Springer
141views Hardware» more  ATVA 2009»
14 years 21 days ago
Formal Verification for High-Assurance Behavioral Synthesis
We present a framework for certifying hardware designs generated through behavioral synthesis, by using formal verification to certify the associated synthesis transformations. We ...
Sandip Ray, Kecheng Hao, Yan Chen, Fei Xie, Jin Ya...
ASPDAC
2007
ACM
81views Hardware» more  ASPDAC 2007»
14 years 21 days ago
LEAF: A System Level Leakage-Aware Floorplanner for SoCs
Abstract-- Process scaling and higher leakage power have resulted in increased power densities and elevated die temperatures. Due to the interdependence of temperature and leakage ...
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal...
ASPDAC
2007
ACM
100views Hardware» more  ASPDAC 2007»
14 years 21 days ago
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning
- For modern processor designs in nanometer technologies, both block and interconnect pipelining are needed to achieve multi-gigahertz clock frequency, but previous approaches cons...
Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong,...
ASPDAC
2007
ACM
92views Hardware» more  ASPDAC 2007»
14 years 21 days ago
Numerical Function Generators Using Edge-Valued Binary Decision Diagrams
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
ASPDAC
2007
ACM
132views Hardware» more  ASPDAC 2007»
14 years 21 days ago
FastRoute 2.0: A High-quality and Efficient Global Router
Because of the increasing dominance of interconnect issues in advanced IC technology, it is desirable to incorporate global routing into early design stages to get accurate interco...
Min Pan, Chris C. N. Chu
ASPDAC
2007
ACM
114views Hardware» more  ASPDAC 2007»
14 years 21 days ago
Automating Logic Rectification by Approximate SPFDs
Yu-Shen Yang, Subarnarekha Sinha, Andreas G. Vener...
ASPDAC
2007
ACM
135views Hardware» more  ASPDAC 2007»
14 years 21 days ago
Architectural Optimizations for Text to Speech Synthesis in Embedded Systems
Abstract-- The increasing processing power of embedded devices have created the scope for certain applications that could previously be executed in desktop environments only, to mi...
Soumyajit Dey, Monu Kedia, Anupam Basu
ASPDAC
2007
ACM
82views Hardware» more  ASPDAC 2007»
14 years 21 days ago
Low-Power High-Speed 180-nm CMOS Clock Drivers
- The power dissipation (PT) and delay time (tdT) of a CMOS clock driver were minimized. Eight test circuits, each of which has 2 two-stage clock drivers, and a register array were...
Tadayoshi Enomoto, Suguru Nagayama, Nobuaki Kobaya...