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ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
14 years 21 days ago
Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation
In this paper, we present a method for generating checker circuits from sequential-extended regular expressions (SEREs). Such sequences form the core of increasingly-used Assertion...
Marc Boule, Zeljko Zilic
ASPDAC
2007
ACM
109views Hardware» more  ASPDAC 2007»
14 years 21 days ago
Communication Architecture Synthesis of Cascaded Bus Matrix
Jun-hee Yoo, Dongwook Lee, Sungjoo Yoo, Kiyoung Ch...
ASPDAC
2007
ACM
87views Hardware» more  ASPDAC 2007»
14 years 21 days ago
A Retargetable Software Timing Analyzer Using Architecture Description Language
Xianfeng Li, Abhik Roychoudhury, Tulika Mitra, Pra...
ASPDAC
2007
ACM
121views Hardware» more  ASPDAC 2007»
14 years 21 days ago
Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches
In recent years, several alternative devices have been proposed to deal with inherent limitation of conventional CMOS devices in terms of scalability at nanometer scale geometry. ...
Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab
ASAP
2007
IEEE
133views Hardware» more  ASAP 2007»
14 years 21 days ago
An Efficient Hardware Support for Control Data Validation
Software-based, fine-grain control flow integrity (CFI) validation technique has been proposed to enforce control flow integrity of program execution. By validating every indirect...
Yong-Joon Park, Zhao Zhang, Gyungho Lee
ASAP
2007
IEEE
130views Hardware» more  ASAP 2007»
14 years 21 days ago
A Self-Reconfigurable Implementation of the JPEG Encoder
Dynamic reconfiguration allows to selectively substitute blocks of logic at run-time in order to improve the area efficiency of a FPGA design. This paper presents the design of a ...
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo...
ASAP
2007
IEEE
203views Hardware» more  ASAP 2007»
14 years 21 days ago
Reconfigurable Universal Adder
In this paper we present a novel adder/subtracter arithmetic unit that combines Binary and Binary Code Decimal (BCD) operations. The proposed unit uses effective addition/subtract...
Humberto Calderon, Georgi Gaydadjiev, Stamatis Vas...
ASAP
2007
IEEE
157views Hardware» more  ASAP 2007»
14 years 21 days ago
Automatic Generation and Optimisation of Reconfigurable Financial Monte-Carlo Simulations
Monte-Carlo simulations are used in many applications, such as option pricing and portfolio evaluation. Due to their high computational load and intrinsic parallelism, they are id...
David B. Thomas, Jacob A. Bower, Wayne Luk