Sciweavers

ASAP
2007
IEEE
150views Hardware» more  ASAP 2007»
14 years 21 days ago
Customizing Reconfigurable On-Chip Crossbar Scheduler
We present a design of a customized crossbar scheduler for on-chip networks. The proposed scheduler arbitrates on-demand interconnects, where physical topologies are identical to ...
Jae Young Hur, Todor Stefanov, Stephan Wong, Stama...
ARC
2007
Springer
102views Hardware» more  ARC 2007»
14 years 21 days ago
Reconfigurable Hardware Acceleration of Canonical Graph Labelling
Many important algorithms in computational biology and related subjects rely on the ability to extract and to identify sub-graphs of larger graphs; an example is to find common fun...
David B. Thomas, Wayne Luk, Michael Stumpf
ARC
2007
Springer
123views Hardware» more  ARC 2007»
14 years 21 days ago
Multiple Sequence Alignment Using Reconfigurable Computing
The alignment of multiple protein (or DNA) sequences is a current problem in Bioinformatics. ClustalW is the most popular heuristic algorithm for multiple sequence alignment. Pairw...
Carlos R. Erig Lima, Heitor S. Lopes, Maiko R. Mor...
ARC
2007
Springer
120views Hardware» more  ARC 2007»
14 years 21 days ago
Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs
Abstract. Conventional rigid router-based networks on chip incur certain overheads due to huge occupied logic resources and topology embedding, i.e., the mapping of a logical netwo...
Jae Young Hur, Stephan Wong, Stamatis Vassiliadis
ARC
2007
Springer
140views Hardware» more  ARC 2007»
14 years 21 days ago
Reconfigurable Computing for Accelerating Protein Folding Simulations
Abstract. This paper presents a methodology for the design of a reconfigurable computing system applied to a complex problem in molecular Biology: the protein folding problem. An e...
Nilton B. Armstrong, Heitor S. Lopes, Carlos R. Er...
ARC
2007
Springer
150views Hardware» more  ARC 2007»
14 years 21 days ago
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Be...
ARC
2007
Springer
118views Hardware» more  ARC 2007»
14 years 21 days ago
Simulation of the Dynamic Behavior of One-Dimensional Cellular Automata Using Reconfigurable Computing
This paper presents the implementation of an environment for the evolution of one-dimensional cellular automata using a reconfigurable logic device. This configware is aimed at eva...
Wagner Rodrigo Weinert, César Manuel Vargas...
ASPDAC
2009
ACM
112views Hardware» more  ASPDAC 2009»
14 years 21 days ago
Compiler-managed register file protection for energy-efficient soft error reduction
Abstract-- For embedded systems where neither energy nor reliability can be easily sacrificed, we present an energy efficient soft error protection scheme for register files (RF). ...
Jongeun Lee, Aviral Shrivastava
ASPDAC
2009
ACM
141views Hardware» more  ASPDAC 2009»
14 years 21 days ago
Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures
Abstract-- The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri...
ASPDAC
2009
ACM
190views Hardware» more  ASPDAC 2009»
14 years 21 days ago
A reverse-encoding-based on-chip AHB bus tracer for efficient circular buffer utilization
The post-T/pre-T trace refers to the trace captured before/after a target point is reached, respectively. Real time compression of the post-T trace in a circular buffer is a challe...
Fu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang