ASPDAC
2009
ACM
14 years 21 days ago
2009
ACM
The number of vias generated during the global routing stage is a critical factor for the yield of final circuits. However, most global routers only approach the problem by chargin...
ASPDAC
2009
ACM
14 years 21 days ago
2009
ACM
Global routing is an important step for physical design. In this paper, we develop a new global router, NTUgr, that contains three major steps: prerouting, initial routing, and enh...
ASPDAC
2009
ACM
2009
ACM
Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture
14 years 21 days ago
-- Carbon nanotubes (CNTs) and carbon nanotube field effect transistors (CNFETs) have demonstrated extraordinary properties and are widely accepted as the building blocks of next g...
ASAP
2009
IEEE
14 years 21 days ago
2009
IEEE
ARC
2009
Springer
14 years 21 days ago
2009
Springer
Run-time reconfigurable FPGAs are powerful platforms for realising software-defined radio systems. This paper introduces a parametric approach to designing such systems based on ap...
AICCSA
2007
IEEE
14 years 22 days ago
2007
IEEE
Two strategies are used for the allocation of jobs to processors connected by mesh topologies: contiguous allocation and non-contiguous allocation. In noncontiguous allocation, a ...
AICCSA
2007
IEEE
14 years 22 days ago
2007
IEEE
Abstract-- This paper presents an artificial neural networks approach to estimate the indicated torque of a single-cylinder diesel engine from crank shaft angular position and velo...
AICCSA
2007
IEEE
14 years 22 days ago
2007
IEEE
In this paper the Karnaugh and Quine-McCluskey methods are used for symbolic classification problem, and then these methods are compared with other famous available methods. Becau...
AHS
2007
IEEE
14 years 22 days ago
2007
IEEE
In this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. The inputs of...
AHS
2007
IEEE
14 years 22 days ago
2007
IEEE
This paper presents a mechanism for the separation of control and data flow in NoC-based SoCs consisting of multiple heterogeneous reconfigurable IP cores. This mechanism enables ...