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AHS
2007
IEEE
251views Hardware» more  AHS 2007»
14 years 22 days ago
System Level Modelling of Reconfigurable FFT Architecture for System-on-Chip Design
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity...
Ali Ahmadinia, Balal Ahmad, Tughrul Arslan
ACSD
2007
IEEE
140views Hardware» more  ACSD 2007»
14 years 22 days ago
Synthesis of Petri Nets from Finite Partial Languages
In this paper we present two algorithms that effectively synthesize a finite place/transition Petri net (p/t-net) from a finite set of labeled partial orders (a finite partial lang...
Robert Lorenz, Robin Bergenthum, Jörg Desel, ...
ACSD
2007
IEEE
109views Hardware» more  ACSD 2007»
14 years 22 days ago
Efficient Automatic Resolution of Encoding Conflicts Using STG Unfoldings
Synthesis of asynchronous circuits from Signal Transition Graphs (STGs) involves resolution of state encoding conflicts by means of refining the STG specification. In this paper, ...
Victor Khomenko
ACSD
2009
IEEE
87views Hardware» more  ACSD 2009»
14 years 22 days ago
Saving Space in a Time Efficient Simulation Algorithm
A number of algorithms are available for computing the simulation relation on Kripke structures and on labelled transition systems representing concurrent systems. Among them, the...
Silvia Crafa, Francesco Ranzato, Francesco Tapparo
ECMDAFA
2010
Springer
141views Hardware» more  ECMDAFA 2010»
14 years 22 days ago
Comparing Approaches to Implement Feature Model Composition
Abstract. The use of Feature Models (FMs) to define the valid combinations of features in Software Product Lines (SPL) is becoming commonplace. To enhance the scalability of FMs, ...
Mathieu Acher, Philippe Collet, Philippe Lahire, R...
DATE
2010
IEEE
175views Hardware» more  DATE 2010»
14 years 22 days ago
Approximate logic synthesis for error tolerant applications
─ Error tolerance formally captures the notion that – for a wide variety of applications including audio, video, graphics, and wireless communications – a defective chip that...
Doochul Shin, Sandeep K. Gupta
CPE
1998
Springer
108views Hardware» more  CPE 1998»
14 years 22 days ago
Edinet: An Execution Driven Interconnection Network Simulator for DSM Systems
Jose Flich, Pedro López, Manuel P. Malumbre...
SIGMETRICS
1990
ACM
129views Hardware» more  SIGMETRICS 1990»
14 years 22 days ago
An Analytical Model of Multistage Interconnection Networks
Multiprocessors require an interconnection network to connect processors with memory modules. The performance of the interconnection network can have a large effect upon overall s...
Darryl L. Willick, Derek L. Eager
SIGMETRICS
1990
ACM
14 years 22 days ago
Ease: An Environment for Architecture Study and Experimentation
Jack W. Davidson, David B. Whalley
SIGMETRICS
1990
ACM
14 years 22 days ago
An Evaluation of Redundant Arrays of Disks Using an Amdahl 5890
Recently we presented several disk array architectures designed to increase the data rate and I/O rate of supercomputing applications, transaction processing, and file systems [Pat...
Peter M. Chen, Garth A. Gibson, Randy H. Katz, Dav...