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ICCAD
1990
IEEE
51views Hardware» more  ICCAD 1990»
14 years 23 days ago
A Detailed Router for Field-Programmable Gate Arrays
Stephen Dean Brown, Jonathan Rose, Zvonko G. Vrane...
SIGMETRICS
1992
ACM
14 years 23 days ago
Factors in the Performance of the AN1 Computer Network
Susan S. Owicki, Anna R. Karlin
SIGMETRICS
1992
ACM
145views Hardware» more  SIGMETRICS 1992»
14 years 23 days ago
Analysis of the Generalized Clock Buffer Replacement Scheme for Database Transaction Processing
The CLOCK algorithm is a popular buffer replacement algorithm becauseof its simplicity and its ability to approximate the performance of the Least Recently Used (LRU) replacement ...
Victor F. Nicola, Asit Dan, Daniel M. Dias
SIGMETRICS
1992
ACM
128views Hardware» more  SIGMETRICS 1992»
14 years 23 days ago
MemSpy: Analyzing Memory System Bottlenecks in Programs
To cope with the increasing difference between processor and main memory speeds, modern computer systems use deep memory hierarchies. In the presence of such hierarchies, the perf...
Margaret Martonosi, Anoop Gupta, Thomas E. Anderso...
CAV
1990
Springer
114views Hardware» more  CAV 1990»
14 years 23 days ago
Formal Verification of Digital Circuits Using Symbolic Ternary System Models
Ternary system modeling involves extending the traditional set of binary values
Randal E. Bryant, Carl-Johan H. Seger
AVMFSS
1989
236views Hardware» more  AVMFSS 1989»
14 years 23 days ago
Temporal Logic Case Study
William G. Wood
NIXDORF
1992
127views Hardware» more  NIXDORF 1992»
14 years 23 days ago
Three non Conventional Paradigms of Parallel Computation
Abstract. We consider three paradigms of computation where the bene ts of a parallel solution are greater than usual. Paradigm 1 works on a time-varying input data set, whose size ...
Fabrizio Luccio, Linda Pagli, Geppino Pucci
NIXDORF
1992
116views Hardware» more  NIXDORF 1992»
14 years 23 days ago
Programmable Active Memories: A Performance Assessment
We present some quantitative performance measurements for the computing power of Programmable Active Memories (PAM), as introduced by [2]. Based on Field Programmable Gate Array (...
Patrice Bertin, Didier Roncin, Jean Vuillemin
MICRO
1992
IEEE
128views Hardware» more  MICRO 1992»
14 years 23 days ago
MISC: a Multiple Instruction Stream Computer
This paper describes a single chip Multiple Instruction Stream Computer (MISC) capable of extracting instruction level parallelism from a broad spectrum of programs. The MISC arch...
Gary S. Tyson, Matthew K. Farrens, Andrew R. Plesz...
MICRO
1992
IEEE
133views Hardware» more  MICRO 1992»
14 years 23 days ago
Code generation schema for modulo scheduled loops
Software pipelining is an important instruction scheduling technique for efficiently overlapping successive iterations of loops and executing them in parallel. Modulo scheduling i...
B. Ramakrishna Rau, Michael S. Schlansker, Parthas...