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MICRO
1999
IEEE
98views Hardware» more  MICRO 1999»
14 years 1 months ago
Instruction Fetch Mechanisms for Multipath Execution Processors
Branch mispredictions can have a major performance impact on high-performance processors. Multipath execution has recently been introduced to help limit the misprediction penaltie...
Artur Klauser, Dirk Grunwald
MICRO
1999
IEEE
123views Hardware» more  MICRO 1999»
14 years 1 months ago
Improving Branch Predictors by Correlating on Data Values
Branch predictors typically use combinations of branch PC bits and branch histories to make predictions. Recent improvements in branch predictors have come from reducing the effec...
Timothy H. Heil, Zak Smith, James E. Smith
MICRO
1999
IEEE
110views Hardware» more  MICRO 1999»
14 years 1 months ago
Balance Scheduling: Weighting Branch Tradeoffs in Superblocks
Since there is generally insufficient instruction level parallelism within a single basic block, higher performance is achieved by speculatively scheduling operations in superbloc...
Alexandre E. Eichenberger, Waleed Meleis
MICRO
1999
IEEE
98views Hardware» more  MICRO 1999»
14 years 1 months ago
Access Region Locality for High-Bandwidth Processor Memory System Design
This paper studies an interesting yet less explored behavior of memory access instructions, called access region locality. Unlike the traditional temporal and spatial data localit...
Sangyeun Cho, Pen-Chung Yew, Gyungho Lee
MICRO
1999
IEEE
105views Hardware» more  MICRO 1999»
14 years 1 months ago
DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design
Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that ...
Todd M. Austin
MICRO
1999
IEEE
71views Hardware» more  MICRO 1999»
14 years 1 months ago
Selective Cache Ways: On-Demand Cache Resource Allocation
Increasing levels of microprocessor power dissipation call for new approaches at the architectural level that save energy by better matching of on-chip resources to application re...
David H. Albonesi
MICRO
1999
IEEE
109views Hardware» more  MICRO 1999»
14 years 1 months ago
Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results
Recent studies on value locality reveal that many instructions are frequently executed with a small variety of inputs. This paper proposes an approach that integrates architecture...
Daniel A. Connors, Wen-mei W. Hwu
ITC
1999
IEEE
105views Hardware» more  ITC 1999»
14 years 1 months ago
Finite state machine synthesis with concurrent error detection
A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are...
Chaohuang Zeng, Nirmal R. Saxena, Edward J. McClus...