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ISSS
1999
IEEE
149views Hardware» more  ISSS 1999»
14 years 1 months ago
A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications
Synchronous Dataflow, a subset of dataflow, has proven to be a good match for specifying DSP programs. Because of the limited amount of memory in embedded DSPs, a key problem duri...
Praveen K. Murthy, Shuvra S. Bhattacharyya
ISSS
1999
IEEE
85views Hardware» more  ISSS 1999»
14 years 1 months ago
Efficient Scheduling of DSP Code on Processors with Distributed Register Files
Code generation methods for digital signal processors are increasingly hampered by the combination of tight timing constraints imposed by the algorithms and the limited capacity o...
Bart Mesman, Carlos A. Alba Pinto, Koen Van Eijk
ISSS
1999
IEEE
109views Hardware» more  ISSS 1999»
14 years 1 months ago
Loop Alignment for Memory Accesses Optimization
Portable or embedded systems allow more and more complex applications like multimedia today. These applications and submicronic technologies have made the power consumption criter...
Antoine Fraboulet, Guillaume Huard, Anne Mignotte
ISSS
1999
IEEE
89views Hardware» more  ISSS 1999»
14 years 1 months ago
Loop Scheduling and Partitions for Hiding Memory Latencies
Partition Scheduling with Prefetching (PSP) is a memory latency hiding technique which combines the loop pipelining technique with data prefetching. In PSP, the iteration space is...
Fei Chen, Edwin Hsing-Mean Sha
ISSS
1999
IEEE
131views Hardware» more  ISSS 1999»
14 years 1 months ago
Compressed Code Execution on DSP Architectures
Decreasing the program size has become an important goal in the design of embedded systems target to mass production. This problem has led to a number of efforts aimed at designin...
Paulo Centoducatte, Ricardo Pannain, Guido Araujo
ISSS
1999
IEEE
157views Hardware» more  ISSS 1999»
14 years 1 months ago
Bit-Width Selection for Data-Path Implementations
Specifications of data computations may not necessarily describe the ranges of the intermediate results that can be generated. However, such information is critical to determine t...
Carlos Carreras, Juan A. López, Octavio Nie...
ISSS
1999
IEEE
151views Hardware» more  ISSS 1999»
14 years 1 months ago
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
Jens Horstmannshoff, Heinrich Meyr
ISSS
1999
IEEE
120views Hardware» more  ISSS 1999»
14 years 1 months ago
RTGEN: An Algorithm for Automatic Generation of Reservation Tables from Architectural Descriptions
Abstract--Reservation Tables (RTs) have long been used to detect conflicts between operations that simultaneously access the same architectural resource. Traditionally, these RTs h...
Peter Grun, Ashok Halambi, Nikil D. Dutt, Alexandr...