ISSS
2000
IEEE
14 years 1 months ago
2000
IEEE
Even though high-level hardware synthesis from dataflow graphs becomes popular in designing DSP systems, currently used dataflow models are inefficient to deal with emerging multi...
ISSS
2000
IEEE
14 years 1 months ago
2000
IEEE
ISSS
2000
IEEE
14 years 1 months ago
2000
IEEE
Various system-level core-based power evaluation approaches for core types like microprocessors, caches, main memories, and buses, have been proposed in the past. Approaches for o...
ISSS
2000
IEEE
14 years 1 months ago
2000
IEEE
The Peripheral Virtual Component Interface, or PVCI, is a standard intended to simplify the interfacing of peripheral cores to on-chip buses in a system-on-a-chip, by standardizin...
ISSS
2000
IEEE
14 years 1 months ago
2000
IEEE
ISSS
2000
IEEE
14 years 1 months ago
2000
IEEE
The ever increasing complexity of embedded systems consisting of hardware and software components poses a challenge in verifying their correctness, New verification methods that o...
ISSS
2000
IEEE
14 years 1 months ago
2000
IEEE
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...
ISSS
2000
IEEE
14 years 1 months ago
2000
IEEE
ISSS
2000
IEEE
14 years 1 months ago
2000
IEEE
In high-throughput real-time media processing systems, the communication between processing units is typically specified as multi-dimensional arrays. However, the implementation ...
ISSS
2000
IEEE
14 years 1 months ago
2000
IEEE
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system level design. In the presented design methodology, each node of a data flow gra...